公开(公告)号：US20250159896A1

公开(公告)日：2025-05-15

申请号：US19023364

申请日：2025-01-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer, Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L23/528 ,  H10B41/23 ,  H10B51/30 ,  H10D30/69 ,  H10D64/01 ,  H10D64/68

Abstract: A ferroelectric memory device, a manufacturing method of the ferroelectric memory device and a semiconductor chip are provided. The ferroelectric memory device includes a gate electrode, a ferroelectric layer, a channel layer, first and second blocking layers, and source/drain electrodes. The ferroelectric layer is disposed at a side of the gate electrode. The channel layer is capacitively coupled to the gate electrode through the ferroelectric layer. The first and second blocking layers are disposed between the ferroelectric layer and the channel layer. The second blocking layer is disposed between the first blocking layer and the channel layer. The first and second blocking layers comprise a same material, and the second blocking layer is further incorporated with nitrogen. The source/drain electrodes are disposed at opposite sides of the gate electrode, and electrically connected to the channel layer.

公开(公告)号：US12289890B2

公开(公告)日：2025-04-29

申请号：US17885575

申请日：2022-08-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Song-Fu Liao ,  Kuo-Chang Chiang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L23/52 ,  H01L23/528 ,  H10B51/20 ,  H10D30/01 ,  H10D30/69 ,  H10D64/68

Abstract: A method of fabricating a transistor structure is provided. The method comprises forming a gate electrode in a dielectric layer of an interconnect structure; forming a monolayer on a portion of the dielectric layer laterally spaced from the gate electrode; sequentially forming a ferroelectric layer, a barrier layer and a channel layer on the gate electrode; and forming a source/drain electrode on the channel layer.

公开(公告)号：US12207474B2

公开(公告)日：2025-01-21

申请号：US17987066

申请日：2022-11-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US12089415B2

公开(公告)日：2024-09-10

申请号：US17569988

申请日：2022-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

CPC classification number: H10B51/30 ,  H10B51/20 ,  H10B53/20 ,  H10B53/30

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.

公开(公告)号：US11990400B2

公开(公告)日：2024-05-21

申请号：US17829590

申请日：2022-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ting-Ya Lo ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/5222 ,  H01L21/76802 ,  H01L21/76831 ,  H01L23/5384 ,  H01L23/5386

Abstract: Some embodiments relate to a method for forming an integrated chip, the method includes forming a first conductive wire and a second conductive wire over a substrate. A dielectric structure is formed laterally between the first conductive wire and the second conductive wire. The dielectric structure comprises a first dielectric liner, a dielectric layer disposed between opposing sidewalls of the first dielectric liner, and a void between an upper surface of the first dielectric liner and a lower surface of the dielectric layer. A dielectric capping layer is formed along an upper surface of the dielectric structure. Sidewalls of the dielectric capping layer are aligned with sidewalls of the dielectric structure.

公开(公告)号：US20240113225A1

公开(公告)日：2024-04-04

申请号：US18152157

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wu-Wei Tsai ,  Yan-Yi Chen ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/0847 ,  H01L29/66742

Abstract: A semiconductor device includes a gate, a semiconductor structure, a gate insulating layer, a first source/drain feature and a second source/drain feature. The gate insulating layer is located between the gate and the semiconductor structure. The semiconductor structure includes at least one first metal oxide layer, a first oxide layer, and at least one second metal oxide layer. The first oxide layer is located between the first metal oxide layer and the second metal oxide layer. The first source/drain feature and the second source/drain feature are electrically connected with the semiconductor structure.

公开(公告)号：US11818896B2

公开(公告)日：2023-11-14

申请号：US17873236

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/40 ,  H01L29/51 ,  H10B51/30 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L23/522

CPC classification number: H10B51/30 ,  H01L23/5226 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode arranged over a substrate. A gate dielectric layer is arranged over the gate electrode, and an active structure is arranged over the gate dielectric layer. A source contact and a drain contact are arranged over the active structure. The active structure includes a stack of cocktail layers alternating with first active layers. The cocktail layers include a mixture of a first material and a second material. The first active layers include a third material that is different than the first and second materials. The bottommost layer of the active structure is one of the cocktail layers.

公开(公告)号：US20230260781A1

公开(公告)日：2023-08-17

申请号：US18305639

申请日：2023-04-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Jiun Lin ,  Hai-Ching Chen ,  Tien-I Bao

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/02203 ,  H01L23/5329 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/02362 ,  H01L29/0649

Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.

公开(公告)号：US20230145317A1

公开(公告)日：2023-05-11

申请号：US17569988

申请日：2022-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159

CPC classification number: H01L27/1159

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.

公开(公告)号：US20230038782A1

公开(公告)日：2023-02-09

申请号：US17394757

申请日：2021-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L27/1159

Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.