公开(公告)号：US20170162489A1

公开(公告)日：2017-06-08

申请号：US15438533

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/09 ,  H01L24/29 ,  H01L24/46 ,  H01L24/97 ,  H01L2224/2908 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the hack side of the terminals each include a contact region which lacks the plating layer.

公开(公告)号：US20160071788A1

公开(公告)日：2016-03-10

申请号：US14854651

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L23/29 ,  H01L21/78 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49565 ,  H01L21/4803 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49541 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

公开(公告)号：US11195269B2

公开(公告)日：2021-12-07

申请号：US14671727

申请日：2015-03-27

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: G06T7/00 ,  H01L23/495 ,  H01L23/00 ,  H05K3/34

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

公开(公告)号：US20160181180A1

公开(公告)日：2016-06-23

申请号：US14580836

申请日：2014-12-23

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L25/00 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device (200) comprising a semiconductor chip (201) has an electrically active side (201a) and an opposite electrically inactive side (201b); the active side bordered by an edge having a first length (202a), and the inactive side bordered by a parallel edge having a second length (202b) smaller than the first length; a substrate has an assembly pad (210) bordered by a linear edge having a third length (210a) equal to or smaller than the first length; the inactive chip side attached to the pad so that the edge of the first length is parallel to the edge of the third length; the active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first length.

Abstract translation: 包括半导体芯片（201）的半导体器件（200）具有电活动侧（201a）和相对的电惰性侧（201b）; 所述有源侧由具有第一长度（202a）的边缘边界，并且所述非活动侧由具有小于所述第一长度的第二长度（202b）的平行边缘界定; 衬底具有由具有等于或小于第一长度的第三长度（210a）的线性边缘界定的组装垫（210） 所述非活动芯片侧附接到所述焊盘，使得所述第一长度的边缘平行于所述第三长度的边缘; 当第三长度小于第一长度时，附接芯片的活动侧在焊盘上形成悬垂。

公开(公告)号：US11769247B2

公开(公告)日：2023-09-26

申请号：US17544896

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: G06T7/00 ,  H01L23/495 ,  H01L23/00 ,  H05K3/34

CPC classification number: G06T7/0008 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49568 ,  H01L24/00 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H05K3/3421 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

公开(公告)号：US10580723B2

公开(公告)日：2020-03-03

申请号：US16427172

申请日：2019-05-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals.A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

公开(公告)号：US10366947B2

公开(公告)日：2019-07-30

申请号：US15438533

申请日：2017-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L21/44 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

公开(公告)号：US20150262903A1

公开(公告)日：2015-09-17

申请号：US14215896

申请日：2014-03-17

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/3107 ,  H01L21/4842 ,  H01L21/56 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49565 ,  H01L23/49838 ,  H01L24/97 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/10254 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2224/85

Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

Abstract translation: 半导体器件具有引线框架，其具有焊盘和一排具有可焊接表面在公共平面中的细长引线; 封装引线框架与组装的半导体器件的封装，使公共平面引线表面与相邻引线之间的封装材料未封装和共面，沿着封装边缘定位一排排列的引线; 并且在共同平面表面中切割的封装材料中的凹槽沿着每个引线长度的一部分延伸，具有宽度和宽度的两倍，并且暴露可焊接的引线表面。

公开(公告)号：US20220092767A1

公开(公告)日：2022-03-24

申请号：US17544896

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: G06T7/00 ,  H01L23/495 ,  H01L23/00

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

公开(公告)号：US09768098B2

公开(公告)日：2017-09-19

申请号：US15099864

申请日：2016-04-15

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L29/06 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/85 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.