公开(公告)号：US20240195417A1

公开(公告)日：2024-06-13

申请号：US18525464

申请日：2023-11-30

Applicant: Texas Instruments Incorporated

Inventor： Avinash Shah ,  Kashyap Barot ,  Sreeram Nasum S ,  Kumar Anurag Shrivastava ,  Suvadip Banerjee

IPC: H03K19/017 ,  G05B19/05 ,  H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/01728 ,  G05B19/054 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/018557 ,  H03K19/017572

Abstract: An example apparatus includes: a current mirror having first and second outputs; oscillator circuitry including: a first transistor having a first terminal coupled to the first output of the current mirror, having a second terminal, and having a control terminal; and a second transistor having a first terminal coupled to the first output of the current mirror, having a second terminal coupled to the control terminal and the second terminal of the first transistor, and having a control terminal coupled to the second terminals of the first and second transistors; and current shunt circuitry having a terminal coupled to the second output of the current mirror.

公开(公告)号：US20240113094A1

公开(公告)日：2024-04-04

申请号：US17957847

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Sreeram N. S. ,  Kashyap Barot ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L25/18 ,  H01F27/28 ,  H01F27/29 ,  H01F27/32 ,  H01L23/00 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/323 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/01 ,  H01F2027/2809 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/4809 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/4909

Abstract: A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.

公开(公告)号：US20240112953A1

公开(公告)日：2024-04-04

申请号：US18148231

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Kashyap Barot ,  Viresh Chinchansure ,  Sreeram N S

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.

公开(公告)号：US10978135B2

公开(公告)日：2021-04-13

申请号：US16793447

申请日：2020-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreeram Subramanyam Nasum ,  Niranjan Shankar ,  Kumar Anurag Shrivastava ,  Kashyap Barot

IPC: G11C11/406 ,  G11C11/409 ,  G11C7/10 ,  G11C7/22

Abstract: An encoding and transmitting system for a digital isolator system includes a transmitter for transmitting combined edge indicator signals through an isolation barrier, an encoder for generating the combined edge indicator signals based on first and second signals, a refresh clock generator for generating a refresh clock signal based on the first signal, and a refresh edge generator for masking at least a portion of the refresh clock signal, such that the portion of the refresh clock signal is not reflected in the second signal. The isolation barrier of the digital isolator system may be a capacitive isolation barrier for galvanically isolating a receiver from the transmitter. If desired, the refresh edge generator may include a refresh mask generator, one or more logic gates, and a glitch filter. A method of operating a digital isolator system is also described.

公开(公告)号：US12183672B2

公开(公告)日：2024-12-31

申请号：US17677729

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ujwal Radhakrishna ,  Vinod Rai ,  Yogesh Ramadass ,  Anant Kamath ,  Kashyap Barot

IPC: H01L23/525 ,  H02H3/04

Abstract: A device includes first and second device terminals, a fuse, a first circuit, a first transistor, and a control circuit. The fuse terminal couples to the first device terminal. The first circuit couples to the second fuse terminal. The second fuse terminal has a first voltage. The first transistor has a first control input and first and second current terminals. The first current terminal couples to the second fuse terminal, and the second current terminal couples to the second device terminal. The control circuit: turns “on” the first transistor into a saturation region if the first voltage exceeds a threshold and a current through the fuse exceeds a trip threshold current of the fuse; and turns “on” the first transistor into a linear region if the first voltage exceeds a threshold and a current through the fuse is below the trip threshold current of the fuse.

公开(公告)号：US20240112852A1

公开(公告)日：2024-04-04

申请号：US17957875

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Byron Lovell Williams ,  Kashyap Barot ,  Sreeram N. S. ,  Viresh Chinchansure

IPC: H01F27/32 ,  H01F41/12

CPC classification number: H01F27/324 ,  H01F41/122 ,  H01F2027/329

Abstract: A microelectronic device includes a galvanic isolation component. The galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. The galvanic isolation component further includes a field suppression structure located interior to the lower winding. The field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. A top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. The conductive field deflector is electrically connected to a semiconductor material in a substrate. The lower winding is separated from a substrate by a first dielectric layer. The upper isolation element is separated from the lower winding by a second dielectric layer.

公开(公告)号：US20230378624A1

公开(公告)日：2023-11-23

申请号：US17750659

申请日：2022-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sreeram Subramanyam NASUM ,  Kashyap Barot

IPC: H01P1/36 ,  H04B1/69 ,  H04B1/16

CPC classification number: H01P1/36 ,  H04B1/69 ,  H04B1/16

Abstract: A device includes a transformer having primary windings and secondary windings, and a transmit circuit coupled to the primary windings. The transmit circuit is configured to receive an input signal, and provide a carrier signal to the primary windings responsive to the input signal. The device also includes a receive circuit coupled to the secondary windings. The receive circuit is configured to receive the carrier signal from the secondary windings, and provide an output signal responsive to the carrier signal. The receive circuit includes a variable capacitor coupled in parallel to the secondary windings, and a spread spectrum modulation circuit configured to modulate a capacitance of the variable capacitor.