公开(公告)号：US08815648B1

公开(公告)日：2014-08-26

申请号：US13854400

申请日：2013-04-01

Applicant: Texas Instruments Incorporated

Inventor： Kengo Aoya ,  Shohta Ujiie ,  Kazunori Hayata

IPC: H01L29/66 ,  H01L23/00

CPC classification number: H01L24/85 ,  H01L21/4867 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85065 ,  H01L2224/85207 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/10253 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of assembling semiconductor devices includes applying a metal paste including a plurality of metal particles having an average size less than 50 nanometers and a binder material onto a metal terminal of a package substrate. The metal paste is processed including a heat up step in a reducing gas atmosphere and then a vacuum sintering step at a temperature of at least 200° C. for forming a sintered metal coating. A semiconductor die is attached onto a die attach area of the package substrate. A bond wire is then connected between a bond pad on the semiconductor die and the sintered metal coating on the metal terminal.

Abstract translation: 一种组装半导体器件的方法包括将包含平均尺寸小于50纳米的多个金属颗粒和粘合剂材料的金属膏施加到封装衬底的金属端子上。 处理包括加热步骤在还原气体气氛中的金属糊料，然后在至少200℃的温度下进行真空烧结步骤以形成烧结金属涂层。 将半导体管芯附着到封装衬底的管芯附着区域上。 然后将接合线连接在半导体管芯上的接合焊盘和金属端子上的烧结金属涂层之间。

公开(公告)号：US09536753B2

公开(公告)日：2017-01-03

申请号：US14504971

申请日：2014-10-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yohei Koto ,  Kazunori Hayata ,  Dan Okamoto

IPC: H01L23/48 ,  H01L23/34 ,  H01L23/04 ,  H01L23/52 ,  H01L21/311 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L21/268 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/31111 ,  H01L21/268 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/49517 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04 ,  H01L2224/04042 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82104 ,  H01L2224/92164 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2224/18 ,  H01L2224/45099 ,  H01L2924/20751

Abstract: A packaged integrated circuit (IC) includes a substrate including a first substrate pad disposed on a first side of the substrate, an IC die disposed on the first side of the substrate, and a first insulating layer molded over the IC die and the substrate. The IC die includes a first die pad on a side of the die opposite from a side of the die adjacent to the first side of the substrate. The first insulating layer includes a first channel extending through the first insulating layer to the first substrate pad, a second channel extending through the first insulating layer to the first die pad, conductive paste filling the first channel and in contact with the first substrate pad, and conductive paste filling the second channel and in contact with the die pad.

Abstract translation: 封装集成电路（IC）包括：衬底，其包括设置在衬底的第一侧上的第一衬底焊盘;设置在衬底的第一侧上的IC管芯;以及模制在IC管芯和衬底上的第一绝缘层。 IC管芯包括在模具的与衬底的第一侧相邻的模具侧面上的第一裸片焊盘。 第一绝缘层包括延伸穿过第一绝缘层到第一衬底焊盘的第一沟道，延伸穿过第一绝缘层到第一裸片焊盘的第二沟道，填充第一沟道并与第一衬底焊盘接触的导电膏， 以及填充第二通道并与管芯焊盘接触的导电膏。

公开(公告)号：US20150340324A1

公开(公告)日：2015-11-26

申请号：US14284644

申请日：2014-05-22

Applicant: Texas Instruments Incorporated

Inventor： Kazunori Hayata ,  Yohei Koto ,  Dan Okamoto

IPC: H01L23/544 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/03466 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/27013 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/83815 ,  H01L2224/83855 ,  H01L2924/10158 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package assembly includes a substrate having an upper surface with a die attachment region thereon. A layer of die attachment material is positioned on top of the die attachment region. The semiconductor package assembly also includes an integrated circuit (“IC”) die. The die has a top portion including a laterally extending top wall surface and a plurality of generally vertically extending wall surfaces extending downwardly from the top wall surface. The die has a metallized bottom portion. The bottom portion has at least two metallized laterally extending wall surfaces and a plurality of metallized generally vertically extending connecting surfaces that connect the metallized laterally extending surfaces of the bottom portion. The layer of die attachment material interfaces with one or both of the metallized laterally extending surfaces and the plurality of metallized generally vertically extending connecting wall surfaces.

Abstract translation: 半导体封装组件包括具有上表面的衬底，其上具有管芯附接区域。 一层模具附着材料位于模具附接区域的顶部。 半导体封装组件还包括集成电路（“IC”）管芯。 模具具有顶部，其包括横向延伸的顶壁表面和从顶壁表面向下延伸的多个大致垂直延伸的壁表面。 模具具有金属化的底部部分。 底部具有至少两个金属化横向延伸的壁表面和连接底部的金属化侧向延伸表面的多个金属化的大致垂直延伸的连接表面。 管芯附着材料层与金属化侧向延伸表面中的一个或两个和多个金属化的大体垂直延伸的连接壁表面相接合。

公开(公告)号：US08716068B2

公开(公告)日：2014-05-06

申请号：US14040089

申请日：2013-09-27

Applicant: Texas Instruments Incorporated

Inventor： Darvin R. Edwards ,  Siva P. Gurrum ,  Masood Murtuza ,  Matthew D. Romig ,  Kazunori Hayata

IPC: H01L21/50

CPC classification number: H01L21/56 ,  H01L21/4821 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48739 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/83001 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85001 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In fabricating a semiconductor device first layers are formed of sintered bondable and solderable metal on a carrier strip. The first layers are patterned into first pads and second pads. A set of first pads is surrounding each second pad. The first pads are spaced from the second pad by gaps. The patterned layers are formed of agglomerate metal vertically on the first layers of sintered bondable and solderable metal of the first pads and of the second pad. The second layers are formed of sintered bondable and solderable metal vertically on the layers of agglomerate metal of the first pads.

Abstract translation: 在制造半导体器件中，第一层由载体条上的可烧结的可焊接金属形成。 第一层被图案化成第一衬垫和第二衬垫。 一组第一焊盘围绕每个第二焊盘。 第一焊盘通过间隙与第二焊盘间隔开。 图案化的层由第一焊盘和第二焊盘的可烧结的可焊接和可焊接金属的第一层上垂直形成为聚集体金属。 第二层由可烧结的可焊接和可焊接的金属垂直地形成在第一焊盘的附聚金属层上。