公开(公告)号：US20190027494A1

公开(公告)日：2019-01-24

申请号：US16138619

申请日：2018-09-21

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/423 ,  H01L27/11565 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11575

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20180268902A1

公开(公告)日：2018-09-20

申请号：US15910411

申请日：2018-03-02

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Hiroyasu TANAKA

IPC: G11C16/04 ,  H01L27/11582 ,  G11C19/28 ,  H01L27/11565

CPC classification number: G11C16/0466 ,  G11C19/28 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A storage device includes a circuit on a substrate, electrode layers stacked on the circuit, a channel layer penetrating the electrode layers in a stacking direction, a plate-shaped first wire between the electrode layers and the circuit and electrically connected to the channel layer, a second wire at a level between the circuit and the first wire, a third wire between the circuit and the second wire, a contact plug penetrating the electrode layers and the first wire in the stacking direction and electrically connected to the second wire, and a columnar support body penetrating the electrode layers and the first wire in the stacking direction. The columnar support body has a lower end in contact with the second wire or the third wire. The first wire has a through-via-hole above the second wire, and the contact plug and the columnar support body are disposed inside the through-via-hole.

公开(公告)号：US20200335517A1

公开(公告)日：2020-10-22

申请号：US16918005

申请日：2020-07-01

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20180240814A1

公开(公告)日：2018-08-23

申请号：US15960842

申请日：2018-04-24

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yoshiaki FUKUZUMI ,  Ryota KATSUMATA ,  Masaru KIDOH ,  Masaru KITO ,  Hiroyasu TANAKA ,  Yosuke KOMORI ,  Megumi ISHIDUKI ,  Hideaki AOCHI

IPC: H01L27/11582 ,  H01L27/11573 ,  G11C16/04

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US20210028185A1

公开(公告)日：2021-01-28

申请号：US17071332

申请日：2020-10-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tetsuya FURUKAWA ,  Tomoaki SHINO ,  Mitsuhiro NOGUCHI ,  Shinichi WATANABE ,  Yukio NISHIDA ,  Hiroyasu TANAKA

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51 ,  H01L29/423

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.

公开(公告)号：US20200066743A1

公开(公告)日：2020-02-27

申请号：US16271992

申请日：2019-02-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tetsuya FURUKAWA ,  Tomoaki SHINO ,  Mitsuhiro NOGUCHI ,  Shinichi WATANABE ,  Yukio NISHIDA ,  Hiroyasu TANAKA

IPC: H01L27/11573 ,  H01L27/11526 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.

公开(公告)号：US20210288073A1

公开(公告)日：2021-09-16

申请号：US17335214

申请日：2021-06-01

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20200273883A1

公开(公告)日：2020-08-27

申请号：US16871375

申请日：2020-05-11

Applicant: Toshiba Memory Corporation

Inventor： Hiroyasu TANAKA ,  Tomoaki SHINO

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11526

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.

公开(公告)号：US20200043944A1

公开(公告)日：2020-02-06

申请号：US16596892

申请日：2019-10-09

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Shinya ARAI ,  Masaki TSUJI ,  Hideaki AOCHI ,  Hiroyasu TANAKA

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11565 ,  H01L29/423

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US20180083029A1

公开(公告)日：2018-03-22

申请号：US15462424

申请日：2017-03-17

Applicant: Toshiba Memory Corporation

Inventor： Hiroyasu TANAKA ,  Tomoaki SHINO

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11526

CPC classification number: H01L27/11582 ,  H01L27/11526 ,  H01L27/11573

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.