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公开(公告)号:US20210118898A1
公开(公告)日:2021-04-22
申请号:US17113285
申请日:2020-12-07
Applicant: Toshiba Memory Corporation
Inventor: Yoshiaki FUKUZUMI , Hideaki AOCHI , Mie MATSUO , Kenichiro YOSHII , Koichiro SHINDO , Kazushige KAWASAKI , Tomoya SANUKI
IPC: H01L27/11573 , H01L27/11568 , H01L27/11582 , H01L21/18 , H01L21/768 , H01L27/11575 , H01L25/065 , H01L25/18
Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
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公开(公告)号:US20200091174A1
公开(公告)日:2020-03-19
申请号:US16283627
申请日:2019-02-22
Applicant: Toshiba Memory Corporation
Inventor: Tomoya SANUKI , Yusuke HIGASHI , Hideto HORII , Masaki KONDO , Hiroki TOKUHIRA , Hideaki AOCHI
IPC: H01L27/11582 , H01L27/1157 , G11C16/04 , G11C16/26 , G11C16/16
Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.
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公开(公告)号:US20190027494A1
公开(公告)日:2019-01-24
申请号:US16138619
申请日:2018-09-21
Applicant: Toshiba Memory Corporation
Inventor: Yoshiaki FUKUZUMI , Shinya ARAI , Masaki TSUJI , Hideaki AOCHI , Hiroyasu TANAKA
IPC: H01L27/11582 , H01L29/423 , H01L27/11565 , H01L29/792 , H01L29/66 , H01L27/11575
Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
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公开(公告)号:US20190088712A1
公开(公告)日:2019-03-21
申请号:US15917145
申请日:2018-03-09
Applicant: Toshiba Memory Corporation
Inventor: Masaki KADO , Tsuyoshi KONDO , Yasuaki OOTERA , Takuya SHIMADA , Michael Arnaud QUINSAT , Nobuyuki UMETSU , Susumu HASHIMOTO , Shiho NAKAMURA , Hideaki AOCHI , Tomoya SANUKI , Shinji MIYANO , Yoshihiro UEDA , Yuichi ITO , Yasuhito YOSHIMIZU
Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first magnetic layer, and a first nonmagnetic layer. The first magnetic member includes a first extension portion and a third portion. The first extension portion extends along a first direction and includes a first portion and a second portion. The third portion is connected to the second portion. A direction from the first portion toward the second portion is aligned with the first direction. At least a portion of the third portion is tilted with respect to the first direction. The first nonmagnetic layer is provided between the first magnetic layer and the at least a portion of the third portion. The first nonmagnetic layer is provided along the at least a portion of the third portion and is tilted with respect to the first direction.
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公开(公告)号:US20200335517A1
公开(公告)日:2020-10-22
申请号:US16918005
申请日:2020-07-01
Applicant: Toshiba Memory Corporation
Inventor: Yoshiaki FUKUZUMI , Shinya ARAI , Masaki TSUJI , Hideaki AOCHI , Hiroyasu TANAKA
IPC: H01L27/11582 , H01L29/66 , H01L29/792 , H01L27/11575 , H01L27/11565 , H01L29/423
Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
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公开(公告)号:US20190088345A1
公开(公告)日:2019-03-21
申请号:US15918344
申请日:2018-03-12
Applicant: Toshiba Memory Corporation
Inventor: Michael Arnaud QUINSAT , Takuya SHIMADA , Susumu HASHIMOTO , Nobuyuki UMETSU , Yasuaki OOTERA , Masaki KADO , Tsuyoshi KONDO , Shiho NAKAMURA , Tomoya SANUKI , Yoshihiro UEDA , Yuichi ITO , Shinji MIYANO , Hideaki AOCHI , Yasuhito YOSHIMIZU
CPC classification number: G11C19/0841 , G11C19/28 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: According to one embodiment, a magnetic memory device includes a first magnetic member, a first electrode, a first magnetic layer, a first non-magnetic layer, a first conductive layer and a controller. The first magnetic member includes a first extending portion and a third magnetic portion. The first extending portion includes first and second magnetic portions. The third magnetic portion is connected with the second magnetic portion. The first electrode is electrically connected with the first magnetic portion. The first non-magnetic layer is provided between the first magnetic layer and at least a part of the third magnetic portion. The first conductive layer includes first and second conductive portions, and a third conductive portion being between the first conductive portion and the second conductive portion. The controller is electrically connected with the first electrode, the first magnetic layer, the first conductive portion and the second conductive portion.
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公开(公告)号:US20180358373A1
公开(公告)日:2018-12-13
申请号:US16106639
申请日:2018-08-21
Applicant: Toshiba Memory Corporation
Inventor: Yoshiaki FUKUZUMI , Hideaki AOCHI
IPC: H01L27/11573 , H01L27/11568 , H01L21/768 , H01L21/18 , H01L27/11582
CPC classification number: H01L27/11573 , H01L21/185 , H01L21/76898 , H01L24/80 , H01L25/18 , H01L25/50 , H01L27/11568 , H01L27/11582 , H01L2225/06541
Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
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公开(公告)号:US20180240814A1
公开(公告)日:2018-08-23
申请号:US15960842
申请日:2018-04-24
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Yoshiaki FUKUZUMI , Ryota KATSUMATA , Masaru KIDOH , Masaru KITO , Hiroyasu TANAKA , Yosuke KOMORI , Megumi ISHIDUKI , Hideaki AOCHI
IPC: H01L27/11582 , H01L27/11573 , G11C16/04
CPC classification number: H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
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公开(公告)号:US20190333927A1
公开(公告)日:2019-10-31
申请号:US16508577
申请日:2019-07-11
Applicant: Toshiba Memory Corporation
Inventor: Yoshiaki FUKUZUMI , Hideaki AOCHI
IPC: H01L27/11573 , H01L27/11568 , H01L21/768 , H01L21/18 , H01L27/11582
Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
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公开(公告)号:US20190287598A1
公开(公告)日:2019-09-19
申请号:US16128554
申请日:2018-09-12
Applicant: Toshiba Memory Corporation
Inventor: Takuya SHIMADA , Yasuaki OOTERA , Tsuyoshi KONDO , Nobuyuki UMETSU , Michael Arnaud QUINSAT , Masaki KADO , Susumu HASHIMOTO , Shiho NAKAMURA , Hideaki AOCHI , Tomoya SANUKI , Shinji MIYANO , Yoshihiro UEDA , Yuichi ITO , Yasuhito YOSHIMIZU
Abstract: According to one embodiment, a magnetic memory device includes a first memory portion, a first conductive portion, a first interconnection, and a controller. The first memory portion includes a first magnetic portion including a first portion and a second portion, a first magnetic layer, and a first nonmagnetic layer provided between the second portion and the first magnetic layer. The first conductive portion is electrically connected to the first portion. The first interconnection is electrically connected to the first magnetic layer. The controller is electrically connected to the first conductive portion and the first interconnection. The controller applies a first pulse having a first pulse height and a first pulse length between the first conductive portion and the first interconnection in a first write operation and applies a second pulse having a second pulse height and a second pulse length in a first shift operation.
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