公开(公告)号：US10832742B2

公开(公告)日：2020-11-10

申请号：US16549844

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Masumi Saitoh ,  Kiwamu Sakuma

IPC: G11C5/06 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor storage device includes a first wire extending in a first direction from a first end to a second end, a plurality of second wires spaced from each other in the first direction and extending in a second direction intersecting the first direction, and a plurality of memory films spaced from each other along the first wire from the first end to the second end and respectively being between the first wire and a second wire of the plurality of second wires. A first memory film of the plurality is at position along the first wire that is between a position of a second memory film and the first end. A contact area between the second memory film and the first wire is greater than a contact area between the first memory film and the first wire.

公开(公告)号：US10446227B2

公开(公告)日：2019-10-15

申请号：US15911413

申请日：2018-03-05

Applicant: Toshiba Memory Corporation

Inventor： Kensuke Ota ,  Masamichi Suzuki ,  Reika Ichihara

IPC: G11C13/00 ,  G11C7/18 ,  G11C11/56

Abstract: According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.

公开(公告)号：US10347650B1

公开(公告)日：2019-07-09

申请号：US16058210

申请日：2018-08-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kiwamu Sakuma ,  Kensuke Ota ,  Masumi Saitoh

IPC: H01L29/76 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/24 ,  H01L29/786 ,  H01L29/04 ,  H01L29/423

Abstract: A semiconductor memory device includes: a substrate; a memory cell array including memory cells arranged in a first direction intersecting a surface of the substrate; an insulating layer covering the memory cell array; and a transistor provided on the insulating layer. The transistor includes: first and second semiconductor layers provided on the insulating layer; a gate electrode provided between the first and second semiconductor layers, one end in the first direction of the gate electrode being closer to the substrate than the first and second semiconductor layers; a gate insulating film provided on the one end and on side surfaces of the gate electrode; and a third semiconductor layer facing the one end and the side surfaces of the gate electrode. The third semiconductor layer includes a crystal grain larger than a shortest distance between the insulating layer and the gate insulating film.

公开(公告)号：US10312289B1

公开(公告)日：2019-06-04

申请号：US16040671

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Masumi Saitoh

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00 ,  H01L23/528

Abstract: A semiconductor memory device comprises a substrate, a plurality of first wirings arranged in a first direction crossing a surface of the substrate, a second wiring extending in the first direction, a variable resistance film provided between the first wiring and the second wiring, a third wiring extending in a second direction crossing the first direction, a select transistor provided between an end of the second wiring and the third wiring. In addition, the semiconductor memory device comprises a chalcogen layer provided at at least a position between the end of the second wiring and the select transistor, and, a position between the third wiring and the select transistor.

公开(公告)号：US10658579B2

公开(公告)日：2020-05-19

申请号：US16290546

申请日：2019-03-01

Applicant: Toshiba Memory Corporation

Inventor： Kensuke Ota ,  Yoko Yoshimura ,  Yoshihiko Moriyama

IPC: H01L45/00 ,  H01L27/24

Abstract: A storage device includes a first conductive layer and a second conductive layer, with an intermediate layer therebetween. The intermediate layer includes a first and second compound regions. The first compound region includes first and second adjacent portions and the second compound region includes third and fourth adjacent portions. Electrical resistance between the first and second conductive layers changes according to a polarity applied across the intermediate layer. In a first polarity state, a concentration of a first element in the first portion is higher than a concentration of the first element in the second portion of the first compound region. A thickness of the third portion in the first polarity state is greater than the thickness of the fourth portion in the first polarity state.

公开(公告)号：US09780170B2

公开(公告)日：2017-10-03

申请号：US15204364

申请日：2016-07-07

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Toshifumi Irisawa ,  Tomoya Kawai ,  Daisuke Matsushita ,  Tsutomu Tezuka

IPC: H01L29/10 ,  H01L29/24 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/10 ,  G11C5/02 ,  G11C16/04 ,  G11C16/14

CPC classification number: H01L29/1037 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/7926

Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.

公开(公告)号：US20200265872A1

公开(公告)日：2020-08-20

申请号：US16549844

申请日：2019-08-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Masumi Saitoh ,  Kiwamu Sakuma

IPC: G11C5/06 ,  H01L27/24 ,  H01L45/00

Abstract: A semiconductor storage device includes a first wire extending in a first direction from a first end to a second end, a plurality of second wires spaced from each other in the first direction and extending in a second direction intersecting the first direction, and a plurality of memory films spaced from each other along the first wire from the first end to the second end and respectively being between the first wire and a second wire of the plurality of second wires. A first memory film of the plurality is at position along the first wire that is between a position of a second memory film and the first end. A contact area between the second memory film and the first wire is greater than a contact area between the first memory film and the first wire.

公开(公告)号：US09825096B2

公开(公告)日：2017-11-21

申请号：US14747215

申请日：2015-06-23

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kensuke Ota ,  Masumi Saitoh

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226

Abstract: According to one embodiment, a resistance change memory includes a first conductive line, a second conductive line provided above the first conductive line, and extending in a first direction, a third conductive line extending in a second direction intersecting the first direction, a select transistor provided between the first and third conductive lines, and a resistance change layer provided between the second and third conductive lines.