公开(公告)号：US20190237581A1

公开(公告)日：2019-08-01

申请号：US16122834

申请日：2018-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Nobuyoshi SAITO ,  Tomomasa UEDA ,  Kentaro MIURA ,  Keiji IKEDA ,  Tsutomu TEZUKA

IPC: H01L29/786 ,  H01L27/108 ,  H01L21/02 ,  H01L29/66

Abstract: According to one embodiment, a transistor includes first to third conductors, first and second oxide semiconductors, and a gate insulating film. The first and second conductors are stacked via an insulator above a substrate. The first oxide semiconductor is formed on the first conductor. The second oxide semiconductor is formed on the first oxide semiconductor. The second oxide semiconductor have a pillar shape through the second conductor along a first direction crossing a surface of the substrate. The second oxide semiconductor is different from the first oxide semiconductor. The gate insulating film is formed between the second conductor and the second oxide semiconductor. The third conductor is formed on the second oxide semiconductor.

公开(公告)号：US20180350829A1

公开(公告)日：2018-12-06

申请号：US16041460

申请日：2018-07-20

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Tsutomu TEZUKA ,  Fumitaka ARAI ,  Keiji IKEDA ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Chika TANAKA ,  Kentaro MIURA ,  Tomoaki SAWABE

IPC: H01L27/11568 ,  G11C16/04 ,  G11C5/06 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C5/06 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.

公开(公告)号：US20180331116A1

公开(公告)日：2018-11-15

申请号：US16041577

申请日：2018-07-20

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu TEZUKA ,  Fumitaka ARAI ,  Keiji IKEDA ,  Tomomasa UEDA ,  Nobuyoshi SAITO ,  Chika TANAKA ,  Kentaro MIURA ,  Tomoaki SAWABE

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C7/18 ,  G11C8/14

CPC classification number: H01L27/11578 ,  G11C7/18 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/4234

Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.

公开(公告)号：US20180269217A1

公开(公告)日：2018-09-20

申请号：US15698077

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Kentaro MIURA ,  Tomomasa Ueda ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L27/11524 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/11524 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/786

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.