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公开(公告)号:US20190121232A1
公开(公告)日:2019-04-25
申请号:US16101547
申请日:2018-08-13
Applicant: Toshiba Memory Corporation
Inventor: Tomoaki SAWABE , Shinobu Sugimura , Koji Asakawa
IPC: G03F7/00 , H01L21/308 , H01L21/3065 , H01L21/027 , G03F7/075 , C09C1/30 , C03C17/22 , C03C17/30
Abstract: According to one embodiment, a pattern formation method can include performing a first processing of causing a surface of a first member of a processing body to be hydrophobic. The processing body includes the first member and a second member. The second member is provided at a portion of the first member. The method can include performing a second processing of causing the processing body to contact an atmosphere including a metal compound. The second processing is after the first processing. The method can include performing a third processing of processing the processing body in an atmosphere including at least one selected from the group consisting of water, oxygen, and ozone. The third processing is after the second processing. In addition, the method can include removing, after the third processing, at least a portion of another portion of the first member by using the second member as a mask.
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公开(公告)号:US20200013892A1
公开(公告)日:2020-01-09
申请号:US16351245
申请日:2019-03-12
Applicant: Toshiba Memory Corporation
Inventor: Junji KATAOKA , Tomomasa UEDA , Tomoaki SAWABE , Keiji IKEDA , Nobuyoshi SAITO
IPC: H01L29/786 , H01L29/24 , H01L45/00
Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer and a first layer. The semiconductor layer includes a first portion including a first element and oxygen. The first element includes at least one selected from the group consisting of In, Ga, Zn, Al, Sn, Ti, Si, Ge, Cu, As, and W. The first layer includes a second element including at least one selected from the group consisting of W, Ti, Ta, Mo, Cu, Al, Ag, Hf, Au, Pt, Pd, Ru, Y, V, Cr, Ni, Nb, In, Ga, Zn, and Sn. The first portion includes a first region and a second region. The second region is provided between the first region and the first layer. The first region includes a bond of the first element and oxygen. The second region includes a bond of the first element and a metallic element.
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公开(公告)号:US20190086805A1
公开(公告)日:2019-03-21
申请号:US15919443
申请日:2018-03-13
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Koji ASAKAWA , Naoko KIHARA , Seekei LEE , Norikatsu SASAO , Tomoaki SAWABE , Shinobu SUGIMURA
Abstract: According to one embodiment, a pattern formation material includes a first monomer. The first monomer includes a first molecular chain, a first group, and a second group. The first molecular chain includes a first end and a second end. The first group has an ester bond to the first end. The second group has an ester bond to the second end. The first group is one of acrylic acid or methacrylic acid. The second group is one of acrylic acid or methacrylic acid. The first molecular chain includes a plurality of first elements bonded in a straight chain configuration. The first elements are one of carbon or oxygen. The number of the first elements is 6 or more. A film including the first monomer is caused to absorb a metal compound including a metallic element.
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公开(公告)号:US20200303554A1
公开(公告)日:2020-09-24
申请号:US16563307
申请日:2019-09-06
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Tomoaki SAWABE , Nobuyoshi SAITO , Junji KATAOKA , Tomomasa UEDA , Keiji IKEDA
IPC: H01L29/786 , H01L21/02 , H01L29/51 , H01L29/49
Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.
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公开(公告)号:US20180138048A1
公开(公告)日:2018-05-17
申请号:US15703127
申请日:2017-09-13
Applicant: Toshiba Memory Corporation
Inventor: Tomoaki SAWABE , Shinobu SUGIMURA , Koji ASAKAWA
IPC: H01L21/308 , H01L21/027 , G03F7/00
Abstract: According to one embodiment, a pattern formation method includes forming a structure body on a first surface of a patterning member, the structure body having protrusions and a recess. The protrusions are arranged at a first pitch along a first direction. The first direction is aligned with the first surface. The recess is between the protrusions. The method further includes forming a resin film of a block copolymer on the structure body. The block copolymer includes first portions and second portions. The first and second portions are arranged alternately at a second pitch along the first direction. The structure body includes first and second regions. The first portions are on the first regions. The second portions on the second regions. The method further includes removing the second portions and the second regions, introducing a metal to the first regions, and etching the patterning member using the first regions.
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公开(公告)号:US20190296155A1
公开(公告)日:2019-09-26
申请号:US16103880
申请日:2018-08-14
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Tomoaki SAWABE , Tomomasa UEDA , Keiji IKEDA , Tsutomu TEZUKA , Nobuyoshi SAITO
IPC: H01L29/786 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L27/108 , H01L29/778
Abstract: A semiconductor device of an embodiment includes a first electrode; a second electrode; an oxide semiconductor layer provided between the first electrode and the second electrode and extending in a first direction; a gate electrode surrounding the oxide semiconductor layer; and a first gate insulating layer provided between the gate electrode and the oxide semiconductor layer, the first gate insulating layer surrounding the oxide semiconductor layer, and the first gate insulating layer having a length in the first direction shorter than a length of the oxide semiconductor layer in the first direction.
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公开(公告)号:US20180350829A1
公开(公告)日:2018-12-06
申请号:US16041460
申请日:2018-07-20
Applicant: TOSHIBA MEMORY CORPORATION
Inventor: Tsutomu TEZUKA , Fumitaka ARAI , Keiji IKEDA , Tomomasa UEDA , Nobuyoshi SAITO , Chika TANAKA , Kentaro MIURA , Tomoaki SAWABE
IPC: H01L27/11568 , G11C16/04 , G11C5/06 , H01L29/66 , H01L29/792
CPC classification number: H01L27/11568 , G11C5/06 , G11C11/5671 , G11C16/0466 , G11C16/08 , G11C16/10 , G11C16/26 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
Abstract: According to one embodiment, a memory includes: a member extending in a first direction and including an oxide semiconductor layer including first to third portions arranged in order from the bit line to the source line; first, second and third conductive layers arranged along the first direction and facing the first to third portions, respectively, the first conductive layer including first material, and each of the second and third conductive layer including a second material different from the first material; a memory cell in a first position corresponding to the first portion, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor in a second position corresponding to the second portion; and a second transistor in a third position corresponding to the third portion.
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公开(公告)号:US20180331116A1
公开(公告)日:2018-11-15
申请号:US16041577
申请日:2018-07-20
Applicant: Toshiba Memory Corporation
Inventor: Tsutomu TEZUKA , Fumitaka ARAI , Keiji IKEDA , Tomomasa UEDA , Nobuyoshi SAITO , Chika TANAKA , Kentaro MIURA , Tomoaki SAWABE
IPC: H01L27/11578 , H01L27/1157 , H01L27/11565 , H01L29/423 , G11C16/08 , G11C16/24 , G11C16/04 , G11C7/18 , G11C8/14
CPC classification number: H01L27/11578 , G11C7/18 , G11C8/14 , G11C16/0483 , G11C16/08 , G11C16/24 , H01L27/11565 , H01L27/1157 , H01L29/4234
Abstract: According to one embodiment, a memory includes: a first gate of a first transistor and a second gate electrode of the second transistor facing the a semiconductor layer; an oxide semiconductor layer between the first and second transistors and including first to fifth portions in order; a third gate of a first cell facing the first portion; a fourth gate of a third transistor facing the second portion; a fifth gate of a second cell facing the third portion; a sixth gate of a fourth transistor facing the fourth portion; an interconnect connected to the fifth portion; a source line connected to the first transistor; and a bit line connected to the second transistor. A material of the third gate is different from a material of the fourth gate.
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