公开(公告)号：US09793293B1

公开(公告)日：2017-10-17

申请号：US15461509

申请日：2017-03-17

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Shinichi Nakao ,  Yasuhito Yoshimizu ,  Kouji Matsuo ,  Kei Watanabe ,  Atsuko Sakata

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565 ,  H01L21/321 ,  H01L21/283

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/32105 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

Abstract: A semiconductor device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed; a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and a first separation region provided in the stacked body and extending in a first direction. The stacked body includes a memory cell array and a staircase portion arranged in the first direction, the memory cell array including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged along the first direction. The first separation region includes a first portion and a second portion in the staircase portion, the first portion having a first width in a second direction crossing the first direction, and the second portion having a second width in the second direction. The second width is narrower than the first width.

公开(公告)号：US10930665B2

公开(公告)日：2021-02-23

申请号：US16536552

申请日：2019-08-09

Applicant: Toshiba Memory Corporation

Inventor： Kosuke Horibe ,  Kei Watanabe ,  Toshiyuki Sasaki ,  Tomo Hasegawa ,  Soichi Yamazaki ,  Keisuke Kikutani ,  Jun Nishimura ,  Hisashi Harada ,  Hideyuki Kinoshita

IPC: H01L27/11578 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11573

Abstract: A semiconductor device of an embodiment includes a control circuit arranged on a substrate, a first conductive layer arranged on the control circuit and containing a first element as a main component, a multilayer structure arranged on the first conductive layer and configured such that multiple second conductive layers and multiple insulating layers are alternately stacked on each other, a memory layer penetrating the multilayer structure and reaching the first conductive layer at a bottom portion, a first layer arranged between the control circuit and the first conductive layer and containing the first element as a main component, and a second layer arranged between the control circuit and the first layer and containing, as a main component, a second element different from the first element.

公开(公告)号：US10763122B2

公开(公告)日：2020-09-01

申请号：US15695918

申请日：2017-09-05

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Soichi Yamazaki ,  Kazuhito Furumoto ,  Kosuke Horibe ,  Keisuke Kikutani ,  Atsuko Sakata ,  Junichi Wada ,  Toshiyuki Sasaki

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/033 ,  H01L27/11582 ,  H01L27/1157

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.

公开(公告)号：US09754793B2

公开(公告)日：2017-09-05

申请号：US15376336

申请日：2016-12-12

Applicant: Toshiba Memory Corporation

Inventor： Shinichi Nakao ,  Shunsuke Ochiai ,  Yusuke Oshiki ,  Kei Watanabe ,  Mitsuhiro Omura ,  Kosuke Horibe ,  Atsuko Sakata ,  Junichi Wada ,  Soichi Yamazaki ,  Masayuki Kitamura ,  Yuya Matsubara

IPC: H01L21/336 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/11582

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/11582 ,  H01L28/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten being not less than 30%, patterning the mask layer, and performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the layer to be etched.