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    Semiconductor circuit for arithmetic processing and arithmetic processing method
    1.
    发明授权
    Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
    用于算术处理和算术处理方法的半导体电路

    公开(公告)号：US07296048B2

    公开(公告)日：2007-11-13

    申请号：US10641788

    申请日：2003-08-15

    申请人： Tadahiro Ohmi ,  Makoto Imai ,  Toshiyuki Nozawa ,  Masanori Fujibayashi ,  Koji Kotani ,  Tadashi Shibata ,  Takahisa Nitta

    发明人： Tadahiro Ohmi ,  Makoto Imai ,  Toshiyuki Nozawa ,  Masanori Fujibayashi ,  Koji Kotani ,  Tadashi Shibata ,  Takahisa Nitta

    IPC分类号： G06F7/52

    CPC分类号： G06F7/4824 ,  G06F7/506

    摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing.There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1–3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.

    摘要翻译： 提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。 提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路 用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

    Semiconductor circuit for arithmetic processing and arithmetic processing method
    2.
    发明申请
    Semiconductor circuit for arithmetic processing and arithmetic processing method 失效
    用于算术处理和算术处理方法的半导体电路

    公开(公告)号：US20050080835A1

    公开(公告)日：2005-04-14

    申请号：US10641788

    申请日：2003-08-15

    申请人： Tadahiro Ohmi ,  Makoto Imai ,  Toshiyuki Nozawa ,  Masanori Fujibayashi ,  Koji Kotani ,  Tadashi Shibata ,  Takahisa Nitta

    发明人： Tadahiro Ohmi ,  Makoto Imai ,  Toshiyuki Nozawa ,  Masanori Fujibayashi ,  Koji Kotani ,  Tadashi Shibata ,  Takahisa Nitta

    IPC分类号： G06F7/00 ,  G06F7/48 ,  G06F7/50 ,  G06F7/506

    CPC分类号： G06F7/4824 ,  G06F7/506

    摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data, and this computing unit computes input digit data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.

    摘要翻译： 提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。 提供了一种用于计算输入数据的计算单元，该计算单元在计算时间单位内计算输入数字数据，并输出表示通过计算获得的结果的计算结果，并且如果在计算中产生进位，则计算电路 用于输出表示该进位的进位数据的加法器1-3）和用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

    Semiconductor circuit for arithmetic operation and method of arithmetic operation
    3.
    发明授权
    Semiconductor circuit for arithmetic operation and method of arithmetic operation 失效
    用于算术运算的半导体电路和算术运算方法

    公开(公告)号：US06728745B1

    公开(公告)日：2004-04-27

    申请号：US09581729

    申请日：2000-09-06

    申请人： Tadahiro Ohmi ,  Makoto Imai ,  Toshiyuki Nozawa ,  Masanori Fujibayashi ,  Koji Kotani ,  Tadashi Shibata ,  Takahisa Nitta

    发明人： Tadahiro Ohmi ,  Makoto Imai ,  Toshiyuki Nozawa ,  Masanori Fujibayashi ,  Koji Kotani ,  Tadashi Shibata ,  Takahisa Nitta

    IPC分类号： G06F750

    CPC分类号： G06F7/4824 ,  G06F7/506

    摘要： There is provided a semiconductor circuit for arithmetic processing and an arithmetic processing method that can increase the rate of processing data and reduces the area of a circuit by suppressing wasteful processing. There is provided a computing unit for computing input data within a computation time unit and outputs a computation result representing a result obtained by the computation, and if a carry is generated in the computation a computation circuit (adders 1-3) for outputting carry data representing this carry, and delay means (memory 4) for delaying the computation result from the computation circuit by one computation time unit, are provided.

    摘要翻译： 提供了一种用于算术处理的半导体电路和运算处理方法，其可以通过抑制浪费处理来增加处理数据的速率并减小电路的面积。 提供了一种用于在计算时间单元内计算输入数据的计算单元，并且输出表示通过计算得到的结果的计算结果，并且如果在计算中产生进位，则用于输出进位数据的计算电路（加法器1-3） 并且提供用于将来自计算电路的计算结果延迟一个计算时间单位的延迟装置（存储器4）。

    Semiconductor arithmetic circuit
    4.
    发明授权
    Semiconductor arithmetic circuit 失效
    半导体运算电路

    公开(公告)号：US5917742A

    公开(公告)日：1999-06-29

    申请号：US806744

    申请日：1997-02-27

    申请人： Tadahiro Ohmi ,  Makoto Imai ,  Koji Kotani ,  Tadashi Shibata

    发明人： Tadahiro Ohmi ,  Makoto Imai ,  Koji Kotani ,  Tadashi Shibata

    IPC分类号： G06F7/509 ,  G06F7/49 ,  G06F7/501 ,  G06G7/14 ,  H01L27/10 ,  H03K19/20 ,  H03M1/00 ,  G06G7/00 ,  G06F7/00

    CPC分类号： G06F7/49

    摘要： A semiconductor arithmetic circuit which realizes multiple-item addition processing at high speed and with a small surface areas The semiconductor arithmetic circuit adds a plurality of data expressed in binary format which is provided with terminals for the simultaneous input of the plurality of data, a mechanism for conducting a batch addition operation with respect to all the bits of the plurality of data, and for generating an analog or multi-valued signal having a linear relationship with the results of this addition and a mechanism for converting the analog or multi-valued signal to a digital signal. The plurality of data comprise bit data signals, and 4 or more of these are subjected to batch addition. A plurality of bit groups including a plurality of connected bits are also subjected to batch addition.

    摘要翻译： 一种半导体运算电路，其以高速实现多项目相加处理并具有小的表面积半导体运算电路将多个以二进制格式表示的数据相加，该多个数据被提供有用于同时输入多个数据的终端， 用于针对所述多个数据的所有位执行批量添加操作，并且用于生成与该相加结果具有线性关系的模拟或多值信号以及用于转换模拟或多值信号的机制 到数字信号。 多个数据包括比特数据信号，其中4个或更多个进行批量添加。 包括多个连接的位的多个位组也被进行批量添加。

    Inductive heating device
    5.
    发明授权
    Inductive heating device 有权
    感应加热装置

    公开(公告)号：US08957354B2

    公开(公告)日：2015-02-17

    申请号：US13123339

    申请日：2009-05-13

    申请人： Atsushi Fujita ,  Makoto Imai ,  Hideki Sadakata ,  Yuta Miura ,  Shinichiro Sumiyoshi

    发明人： Atsushi Fujita ,  Makoto Imai ,  Hideki Sadakata ,  Yuta Miura ,  Shinichiro Sumiyoshi

    IPC分类号： H05B6/04 ,  H05B6/06

    CPC分类号： H05B6/062 ,  H05B2213/05

    摘要： Disclosed is an inductive heating device which can lower losses in the device and readily provide cooling, wherein a controller is operated in a first control mode which controls the operation so that a unipolar first switching element and a unipolar second switching element conduct alternately when one of a bipolar third switching element and a bipolar fourth switching element is conducting and the other is disconnected when an aluminum object to be heated is heated, and in a second control mode in which the conduction of the first switching element and the fourth switching element and the conduction of the second switching element and the third switching element alternate when an iron object to be heated is heated.

    摘要翻译： 公开了一种感应加热装置，其可以降低装置中的损耗并容易地提供冷却，其中控制器以控制操作的第一控制模式操作，使得当单极第一开关元件和单极第二开关元件之一 当加热的铝物体被加热时，双极性第三开关元件和双极性第四开关元件导通，另一个断开，并且在第一控制模式中，第一开关元件和第四开关元件以及 当被加热的铁物体被加热时，第二开关元件和第三开关元件的导通交替。

    SEMICONDUCTOR MODULE
    7.
    发明申请
    SEMICONDUCTOR MODULE 审中-公开
    半导体模块

    公开(公告)号：US20140151872A1

    公开(公告)日：2014-06-05

    申请号：US14095592

    申请日：2013-12-03

    申请人： Takaoki Ogawa ,  Makoto Imai ,  Shizuyasu Matsubayashi

    发明人： Takaoki Ogawa ,  Makoto Imai ,  Shizuyasu Matsubayashi

    IPC分类号： H01L23/40

    CPC分类号： H01L23/4006 ,  H01L25/074 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor module includes semiconductor device, at least one cooler, at least one fastening member. The semiconductor device has a flat shape. The at least one cooler is arranged adjacent to the semiconductor device. The at least one fastening member has a pressure-contact part that is configured to apply a pressure to the at least one cooler. Furthermore, the at least one fastening member fastens a layered body including the semiconductor device and the at least one cooler in a layer direction of the layered body. A dent configured to accommodate the pressure-contact part is provided in the at least one cooler.

    摘要翻译： 半导体模块包括半导体器件，至少一个冷却器，至少一个紧固构件。 半导体器件具有扁平形状。 至少一个冷却器被布置成与半导体器件相邻。 所述至少一个紧固构件具有被配置为向所述至少一个冷却器施加压力的压力接触部分。 此外，至少一个紧固构件在层叠体的层方向上紧固包括半导体装置和至少一个冷却器的层叠体。 构造成容纳压力接触部分的凹陷设置在至少一个冷却器中。

    Power module
    8.
    发明授权
    Power module 有权
    电源模块

    公开(公告)号：US08254133B2

    公开(公告)日：2012-08-28

    申请号：US12663813

    申请日：2008-06-12

    申请人： Makoto Imai

    发明人： Makoto Imai

    IPC分类号： H05K1/14

    CPC分类号： H01L25/072 ,  H01L23/04 ,  H01L23/473 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48157 ,  H01L2224/48464 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： Provided is a power module capable of welding a snubber capacitor without causing melting damage to a resin housing by welding heat. When leads of a snubber capacitor are respectively welded to upper surfaces of the specific portions of a P-pole bus bar and an N-pole bus bar, the welding heat generated at the specific portions of the P-pole bus bar and the N-pole bus bar is respectively radiated from openings, through which the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar are exposed. As a result, the snubber capacitor can be later appended by welding without causing melting damage to the resin housing due to the welding heat. During welding, a separate cooling head is inserted into the openings to forcibly cool the lower surfaces of the specific portions of the P-pole bus bar and the N-pole bus bar respectively, so that the melting damage to a resin housing can be more reliably avoided.

    摘要翻译： 提供了能够焊接缓冲电容器而不会通过焊接热而对树脂壳体造成熔融损伤的电力模块。 当缓冲电容器的引线分别焊接在P极母线和N极母线的特定部分的上表面时，在P极母线和N极母线的特定部分产生的焊接热， 极母线从开口分别辐射，P极母线和N极母线的特定部分的下表面露出。 结果，缓冲电容器可以随后通过焊接而附加，而不会由于焊接热而对树脂壳体造成熔融损坏。 在焊接过程中，将一个单独的冷却头插入开口，以分别强制地冷却P极汇流条和N极汇流条的特定部分的下表面，使得对树脂外壳的熔化损伤可以更多 可靠地避免。

    IMAGE PICKUP APPARATUS, MANUFACTURING METHOD THEREOF, AND MOBILE TERMINAL
    10.
    发明申请
    IMAGE PICKUP APPARATUS, MANUFACTURING METHOD THEREOF, AND MOBILE TERMINAL 审中-公开
    图像拾取装置，其制造方法和移动终端

    公开(公告)号：US20100025792A1

    公开(公告)日：2010-02-04

    申请号：US12521092

    申请日：2008-01-09

    申请人： Kiyohiko Yamada ,  Makoto Imai ,  Hiroshi Nishizawa

    发明人： Kiyohiko Yamada ,  Makoto Imai ,  Hiroshi Nishizawa

    IPC分类号： H01L31/0232 ,  H01L21/50

    CPC分类号： G02B27/0006 ,  G02B13/001 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2257 ,  H01L2924/00

    摘要： Degradation of a picked-up image quality occurs because of entry or a move of dust in the internal space of an image pickup apparatus. An image pickup apparatus for decreasing degradation of the image quality by capturing dust is provided. An image pickup apparatus 18 having a lens block 19 containing a lens 2, a semiconductor image pickup device 4 mounted on one face of a board 1, and a translucent member 5 mounted on an opposite face is characterized in that it has a gap 24 to allow a solution 23 with an adhesive dissolved to penetrate outside an optically effective range outside the space surrounded by the semiconductor image pickup device 4, the translucent member 5, and the board 1.

    摘要翻译： 由于图像拾取装置的内部空间中的灰尘的进入或移动而发生拾取图像质量的降低。 提供一种用于通过捕获灰尘来降低图像质量劣化的图像拾取装置。 具有透镜块19的摄像装置18，安装在基板1的一面上的半导体图像拾取装置4和安装在相对的面上的透光部件5的特征在于，具有间隙24〜 允许具有溶解的粘合剂的溶液23渗透到由半导体图像拾取装置4，半透明构件5和板1包围的空间外部的光学有效范围之外。