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公开(公告)号：US6060778A
公开(公告)日：2000-05-09
申请号：US60981
申请日：1998-04-15
申请人： Tae Sung Jeong , Ki Tae Ryu , Tae Keun Lee , Keun Hyoung Choi , Han Shin Youn , Jum Sook Park
发明人： Tae Sung Jeong , Ki Tae Ryu , Tae Keun Lee , Keun Hyoung Choi , Han Shin Youn , Jum Sook Park
CPC分类号： H01L23/3128 , H01L23/13 , H01L23/36 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49109 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01028 , H01L2924/01039 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/12041 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/15156 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H01L2924/20753 , H01L2924/3025
摘要： Disclosed is a packaged integrated circuit device with high heat dissipation performance and low weight. The packaged integrated circuit device includes an interconnection substrate having at least one layer of conductive trace material and at least one layer of insulating material and also having a first surface and a second surface disposed opposite to the first surface and having a plurality of electrical contacts formed on the second surface. At least one metal thermal conductive layer having a first surface is attached on the first surface of the interconnection substrate and having a second surface exposed to an exterior. A through hole region is formed in the interconnection substrate and the thermal conductive layer. An integrated circuit chip having a first surface exposed to an exterior and having also a second surface with a plurality of bond pads, opposite to the first surface of the integrated circuit chip, is placed within the through hole region. A plurality of bond wires make an electrical connection of the bond pads with the conductive trace layers. The bond wires and the integrated circuit chip are enclosed with an insulating encapsulant material. The through hole region is also filled with the insulating encapsulant material.
摘要翻译： 公开了一种具有高散热性能和低重量的封装集成电路器件。 封装的集成电路器件包括互连衬底，其具有至少一层导电迹线材料和至少一层绝缘材料，并且还具有与第一表面相对设置的第一表面和第二表面，并且具有形成的多个电触头 在第二个表面。 具有第一表面的至少一个金属导热层附着在互连基板的第一表面上并具有暴露于外部的第二表面。 在互连基板和导热层中形成通孔区域。 集成电路芯片具有暴露于外部的第一表面，并且具有与集成电路芯片的第一表面相对的多个接合焊盘的第二表面放置在通孔区域内。 多个接合线使接合焊盘与导电迹线层电连接。 接合线和集成电路芯片用绝缘密封材料封装。 通孔区域也填充有绝缘密封剂材料。
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公开(公告)号：US08124459B2
公开(公告)日：2012-02-28
申请号：US11306806
申请日：2006-01-11
申请人： In Sang Yoon , Han Shin Youn , Jae Soo Lee
发明人： In Sang Yoon , Han Shin Youn , Jae Soo Lee
IPC分类号： H01L21/50
CPC分类号： H01L23/3114 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/49541 , H01L24/81 , H01L2221/68345 , H01L2221/68377 , H01L2224/05571 , H01L2224/05573 , H01L2224/16237 , H01L2224/81141 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30105 , H01L2924/00 , H01L2224/05599
摘要： A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the semiconductor die and the electrical interconnects.
摘要翻译： 提供了一种凸块芯片载体半导体封装系统，包括提供引线框架，在引线框架中形成电路插座，将半导体管芯安装在引线框架上，其中半导体管芯具有连接到电路插座的电互连，并封装成型 复合以覆盖半导体管芯和电互连。
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公开(公告)号：US20070108605A1
公开(公告)日：2007-05-17
申请号：US11306806
申请日：2006-01-11
申请人： In Sang Yoon , Han Shin Youn , Jae Soo Lee
发明人： In Sang Yoon , Han Shin Youn , Jae Soo Lee
IPC分类号： H01L23/48
CPC分类号： H01L23/3114 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/49541 , H01L24/81 , H01L2221/68345 , H01L2221/68377 , H01L2224/05571 , H01L2224/05573 , H01L2224/16237 , H01L2224/81141 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/30105 , H01L2924/00 , H01L2224/05599
摘要： A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the semiconductor die and the electrical interconnects.
摘要翻译： 提供了一种凸块芯片载体半导体封装系统，包括提供引线框架，在引线框架中形成电路插座，将半导体管芯安装在引线框架上，其中半导体管芯具有连接到电路插座的电互连，并封装成型 复合以覆盖半导体管芯和电互连。
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