公开(公告)号：US07253531B1

公开(公告)日：2007-08-07

申请号：US11432373

申请日：2006-05-12

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Ming-Ta Lei ,  Chin-Chiu Hsia

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Ming-Ta Lei ,  Chin-Chiu Hsia

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28

CPC分类号： H01L24/10 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： The invention provides a bonding pad structure. At least one lower circuit layer is disposed overlying the substrate, wherein the lower circuit layer is a layout of circuit under pad. A top circuit layer is disposed overlying the lower circuit layer, wherein the top circuit layer comprises a top interconnect dielectric layer and a top interconnect pattern in the top interconnect dielectric layer. A top connecting layer is disposed overlying the top circuit layer, electrically connecting the top interconnect pattern. A top pad layer is disposed overlying the top connecting layer. A bonding ball is disposed overlying the top pad layer, wherein sides of the top interconnect pattern do not overlap a region extending inwardly and outwardly from a boundary of the bonding ball within distance of about 2.5μm.

摘要翻译： 本发明提供一种焊盘结构。 至少一个下电路层设置在衬底上，其中下电路层是衬底下电路的布局。 顶层电路层设置在下电路层的上方，其中顶层电路层包括顶部互连电介质层和顶部互连电介质层中的顶部互连图案。 顶部连接层设置在顶部电路层上方，电连接顶部互连图案。 顶部衬垫层设置在顶部连接层上。 接合球设置在顶部焊盘层的上方，其中顶部互连图案的侧面不与距接合球的边界向内和向外延伸的区域重叠约2.5μm。

公开(公告)号：US20060246686A1

公开(公告)日：2006-11-02

申请号：US10908142

申请日：2005-04-28

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Chin-Chiu Hsia ,  Mong-Song Liang

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Chin-Chiu Hsia ,  Mong-Song Liang

IPC分类号： H01L21/30 ,  H01L21/4763 ,  H01L21/46

CPC分类号： H01L24/48 ,  H01L21/76804 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2224/45099

摘要： Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for mitigating the diminished chemical bonds between etch-stop layers and other semiconductor device layers. The disclosed methods and structures use different structures and/or processes for some of the etch-stop layers in a device.

摘要翻译： 描述了用于减轻放置在半导体器件层上的机械应力的影响的方法和结构，并且具体公开了用于减轻蚀刻停止层和其它半导体器件层之间减少的化学键的方法和结构。 所公开的方法和结构对于装置中的一些蚀刻停止层使用不同的结构和/或工艺。

公开(公告)号：US20060055007A1

公开(公告)日：2006-03-16

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/552 ,  H01L23/12

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上级桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US07151052B2

公开(公告)日：2006-12-19

申请号：US10908142

申请日：2005-04-28

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Chin-Chiu Hsia ,  Mong-Song Liang

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Chin-Chiu Hsia ,  Mong-Song Liang

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L24/48 ,  H01L21/76804 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2224/45099

摘要： Described are methods and structures for mitigating the effects of mechanical stresses placed on the layers of semiconductor devices, and specifically disclosed are methods and structures for mitigating the diminished chemical bonds between etch-stop layers and other semiconductor device layers. The disclosed methods and structures use different structures and/or processes for some of the etch-stop layers in a device.

摘要翻译： 描述了用于减轻放置在半导体器件层上的机械应力的影响的方法和结构，并且具体公开了用于减轻蚀刻停止层和其它半导体器件层之间减少的化学键的方法和结构。 所公开的方法和结构对于装置中的一些蚀刻停止层使用不同的结构和/或工艺。

公开(公告)号：US07777338B2

公开(公告)日：2010-08-17

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上层电桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US20060055002A1

公开(公告)日：2006-03-16

申请号：US11196184

申请日：2005-08-03

申请人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuo Liang ,  Tai-Chun Huang ,  Chin-Chiu Hsia ,  Mong-Song Liang

发明人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuo Liang ,  Tai-Chun Huang ,  Chin-Chiu Hsia ,  Mong-Song Liang

IPC分类号： H01L23/544 ,  H01L21/30

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of the silicon substrate, wherein the seal ring and the shallow trench isolation prevent die saw induced crack from propagating to the active area when the active area is cut along the scribe line.

摘要翻译： 公开了一种用于改善在硅衬底上的有源区域中制造的电路的可靠性的晶片装置。 在有源区域周围制造密封圈，并且通过蚀刻到硅衬底的一部分中，在密封环和划线之间也形成浅沟槽隔离，其中密封环和浅沟槽隔离防止模锯引起裂纹 当沿着划线切割活动区域时，从传播到有源区域。

公开(公告)号：US20070096092A1

公开(公告)日：2007-05-03

申请号：US11264911

申请日：2005-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。

公开(公告)号：US20050133241A1

公开(公告)日：2005-06-23

申请号：US10742240

申请日：2003-12-18

申请人： Kuan-Shou Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

发明人： Kuan-Shou Chi ,  Tai-Chun Huang ,  Chih-Hsiang Yao

IPC分类号： H01L21/58 ,  H01L21/60 ,  H01L23/02 ,  H05K3/30

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/83121 ,  H01L2224/83191 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/4913 ,  Y10T29/49133 ,  H01L2924/00 ,  H01L2224/48

摘要： A chip orientation and attachment method is disclosed which eliminates or substantially reduces chip damage caused by thermal stress induced by application of a molding compound to the chip and substrate. The chip is attached to the substrate in such a manner that at least one of the following conditions exists: the chip diagonal and the substrate diagonal are in non-aligned relationship, and/or the chip edges are non-parallel with respect to the substrate edges, and/or the chip center is in non-overlapping relationship with respect to the substrate center. The invention includes chip package structures fabricated according to the chip orientation and attachment method.

摘要翻译： 公开了一种芯片取向和附接方法，其消除或基本上减少由于将模塑料施加到芯片和基板而引起的热应力引起的芯片损伤。 芯片以这样的方式附接到基板，使得存在以下条件中的至少一个：芯片对角线和基板对角线处于非对准关系，和/或芯片边缘相对于基板不平行 边缘和/或芯片中心相对于基板中心处于非重叠关系。 本发明包括根据芯片取向和附着方法制造的芯片封装结构。

公开(公告)号：US20050158967A1

公开(公告)日：2005-07-21

申请号：US10761004

申请日：2004-01-20

申请人： Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Hsiang Yao

发明人： Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Hsiang Yao

IPC分类号： H01L21/301 ,  H01L21/46 ,  H01L21/78

CPC分类号： H01L21/78 ,  Y10S438/907

摘要： A method to singulate a circuit die from an integrated circuit wafer is achieved. The method comprises providing an integrated circuit wafer containing a circuit die. The integrated circuit wafer is cut through by performing a single, continuous cut around the perimeter of the circuit die to thereby singulate the circuit die.

摘要翻译： 实现了从集成电路晶片中分离电路管芯的方法。 该方法包括提供包含电路管芯的集成电路晶片。 通过围绕电路管芯的周边执行单个连续的切割来切割集成电路晶片，从而对电路管芯进行分离。

公开(公告)号：US07791070B2

公开(公告)日：2010-09-07

申请号：US11264911

申请日：2005-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

IPC分类号： G01R31/26

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。