公开(公告)号：US07791070B2

公开(公告)日：2010-09-07

申请号：US11264911

申请日：2005-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

IPC分类号： G01R31/26

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。

公开(公告)号：US20060055007A1

公开(公告)日：2006-03-16

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/552 ,  H01L23/12

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上级桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US20070096092A1

公开(公告)日：2007-05-03

申请号：US11264911

申请日：2005-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Kuan-Shou Chi ,  Wen-Kai Wan

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： An outer border, and a seal ring substantially co-extensive with and spaced from the outer border is disclosed. A plurality of fault detection chains extend from adjacent the outer border to within the seal ring. At least a first one of the plurality of fault detection chains includes a contact pad, a first metal feature coupled to the contact pad by a first via in a passivation layer, a second metal feature coupled to the first metal feature by a second via, and a substrate contact coupled to the second metal feature by a third via.

摘要翻译： 公开了一种外边界和与外边界基本上共同并与其间隔开的密封环。 多个故障检测链从邻近的外边界延伸到密封环内。 多个故障检测链中的至少第一个包括接触焊盘，通过钝化层中的第一通孔耦合到接触焊盘的第一金属特征，通过第二通孔耦合到第一金属特征的第二金属特征， 以及通过第三通孔耦合到第二金属特征的衬底接触。

公开(公告)号：US07777338B2

公开(公告)日：2010-08-17

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上层电桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US20060055002A1

公开(公告)日：2006-03-16

申请号：US11196184

申请日：2005-08-03

申请人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuo Liang ,  Tai-Chun Huang ,  Chin-Chiu Hsia ,  Mong-Song Liang

发明人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuo Liang ,  Tai-Chun Huang ,  Chin-Chiu Hsia ,  Mong-Song Liang

IPC分类号： H01L23/544 ,  H01L21/30

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of the silicon substrate, wherein the seal ring and the shallow trench isolation prevent die saw induced crack from propagating to the active area when the active area is cut along the scribe line.

摘要翻译： 公开了一种用于改善在硅衬底上的有源区域中制造的电路的可靠性的晶片装置。 在有源区域周围制造密封圈，并且通过蚀刻到硅衬底的一部分中，在密封环和划线之间也形成浅沟槽隔离，其中密封环和浅沟槽隔离防止模锯引起裂纹 当沿着划线切割活动区域时，从传播到有源区域。

公开(公告)号：US07741714B2

公开(公告)日：2010-06-22

申请号：US10979408

申请日：2004-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Wen-Kai Wan

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02125 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/00012

摘要： A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.

摘要翻译： 用于集成电路芯片的接合焊盘结构在顶部互连级金属层和接合焊盘层之间具有应力缓冲层，以防止焊盘结构对晶片探测和封装冲击的损害。 应力缓冲层是具有选自杨氏模量，硬度，强度和韧性大于顶部互连级金属层或接合焊盘层的性质的导电材料。 为了提高附着力和粘结强度，应力缓冲层的下部可以被修改为嵌入钝化层中的各种形式的环，网或互锁网格结构，或者应力缓冲层可以具有开口 与焊垫层。

公开(公告)号：US20060091536A1

公开(公告)日：2006-05-04

申请号：US10979408

申请日：2004-11-02

申请人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Wen-Kai Wan

发明人： Tai-Chun Huang ,  Chih-Hsiang Yao ,  Wen-Kai Wan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02125 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05076 ,  H01L2224/05083 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05576 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01077 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/00012

摘要： A bond pad structure for an integrated circuit chip has a stress-buffering layer between a top interconnection level metal layer and a bond pad layer to prevent damages to the bond pad structure from wafer probing and packaging impacts. The stress-buffering layer is a conductive material having a property selected from the group consisting of Young's modulus, hardness, strength and toughness greater than the top interconnection level metal layer or the bond pad layer. For improving adhesion and bonding strength, the lower portion of the stress-buffering layer may be modified as various forms of a ring, a mesh or interlocking-grid structures embedded in a passivation layer, alternatively, the stress-buffering layer may has openings filled with the bond pad layer.

摘要翻译： 用于集成电路芯片的接合焊盘结构在顶部互连级金属层和接合焊盘层之间具有应力缓冲层，以防止焊盘结构对晶片探测和封装冲击的损害。 应力缓冲层是具有选自杨氏模量，硬度，强度和韧性大于顶部互连级金属层或接合焊盘层的性质的导电材料。 为了提高附着力和粘结强度，应力缓冲层的下部可以被修改为嵌入钝化层中的各种形式的环，网或互锁网格结构，或者应力缓冲层可以具有开口 与焊垫层。

公开(公告)号：US06831365B1

公开(公告)日：2004-12-14

申请号：US10448656

申请日：2003-05-30

申请人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Tai-Chun Huang ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Tai-Chun Huang ,  Chin-Chiu Hsia

IPC分类号： H01L2348

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and a pattern for reducing interconnect failures are described. The method and pattern are used for a multilevel structure of metal/dielectric/metal. At least one assistant pattern is attached to one metal layer of the multilevel structure. A thermal stress gradient resulting from the assistant pattern can collect vacancies of the metal layer, so as to prevent stress-induced voids from generating at the bottom of a via plug which connects the two metal layers.

摘要翻译： 描述了用于减少互连故障的方法和模式。 该方法和图案用于金属/电介质/金属的多层结构。 至少一个辅助图案附着到多层结构的一个金属层。 由辅助图案产生的热应力梯度可以收集金属层的空位，以防止应力诱导的空隙在连接两个金属层的通孔塞的底部产生。

公开(公告)号：US20080191352A1

公开(公告)日：2008-08-14

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。

公开(公告)号：US07880303B2

公开(公告)日：2011-02-01

申请号：US11706553

申请日：2007-02-13

申请人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

发明人： Chen-Hua Yu ,  Chen-Nan Yeh ,  Chih-Hsiang Yao ,  Wen-Kai Wan ,  Jye-Yen Cheng

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a metallization layer over the semiconductor substrate; a first dielectric layer between the semiconductor substrate and the metallization layer; a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion.

摘要翻译： 集成电路结构包括半导体衬底; 半导体衬底上的金属化层; 在所述半导体衬底和所述金属化层之间的第一介电层; 在所述半导体衬底和所述金属化层之间的第二电介质层，其中所述第二电介质层在所述第一介电层上; 以及具有基本上在第二电介质层中的上部的接触插塞和基本上在第一电介质层中的下部。 接触插塞电连接到金属化层中的金属线。 接触塞在上部和下部之间的界面处是不连续的。