公开(公告)号：US20060055002A1

公开(公告)日：2006-03-16

申请号：US11196184

申请日：2005-08-03

申请人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuo Liang ,  Tai-Chun Huang ,  Chin-Chiu Hsia ,  Mong-Song Liang

发明人： Chih-Hsiang Yao ,  Wen-Kai Wan ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuo Liang ,  Tai-Chun Huang ,  Chin-Chiu Hsia ,  Mong-Song Liang

IPC分类号： H01L23/544 ,  H01L21/30

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A wafer device is disclosed for improving reliability of circuits fabricated in an active area on a silicon substrate. A seal ring is fabricated around the active area, and a shallow trench isolation is also formed between the seal ring and a scribe line by etching into a portion of the silicon substrate, wherein the seal ring and the shallow trench isolation prevent die saw induced crack from propagating to the active area when the active area is cut along the scribe line.

摘要翻译： 公开了一种用于改善在硅衬底上的有源区域中制造的电路的可靠性的晶片装置。 在有源区域周围制造密封圈，并且通过蚀刻到硅衬底的一部分中，在密封环和划线之间也形成浅沟槽隔离，其中密封环和浅沟槽隔离防止模锯引起裂纹 当沿着划线切割活动区域时，从传播到有源区域。

公开(公告)号：US20060055007A1

公开(公告)日：2006-03-16

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/552 ,  H01L23/12

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上级桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US07777338B2

公开(公告)日：2010-08-17

申请号：US10940504

申请日：2004-09-13

申请人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

发明人： Chih-Hsiang Yao ,  Tai-Chun Huang ,  Kuan-Shou Chi ,  Chih-Cherng Jeng ,  Ming-Shuoh Liang ,  Wen-Kai Wan ,  Chin-Chiu Hsia

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  B28D5/0011 ,  H01L21/76224 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

摘要翻译： 公开了用于保护集成电路芯片的核心电路区域的密封环结构。 密封圈结构包括具有桥接子层和插塞子层的金属化层。 在集成电路芯片的外围边缘和核心电路区域之间的预定位置处，在桥接子层上形成上层电桥。 在与上层桥接器基本对准的插头子级上形成有较低级别的桥，其中下级桥具有与上级桥基本相同的宽度。

公开(公告)号：US08860101B2

公开(公告)日：2014-10-14

申请号：US13406363

申请日：2012-02-27

申请人： Lan Fang Chang ,  Ching-Hwanq Su ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  Fu-Sheng Guo

发明人： Lan Fang Chang ,  Ching-Hwanq Su ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  Fu-Sheng Guo

IPC分类号： H01L31/062

CPC分类号： H01L31/103 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.

摘要翻译： 提供了一种用于减少感光二极管之间串扰的系统和方法。 在一个实施方案中，包含第一浓度的掺杂剂的隔离区位于感光二极管之间。 感光二极管具有小于掺杂剂的第一浓度的掺杂剂的第二浓度，这有助于防止光敏二极管扩散以形成感光二极管之间不期望的串扰的电势路径。

公开(公告)号：US20130207220A1

公开(公告)日：2013-08-15

申请号：US13406363

申请日：2012-02-27

申请人： Lan Fang Chang ,  Ching-Hwanq Su ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  Fu-Sheng Guo

发明人： Lan Fang Chang ,  Ching-Hwanq Su ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  Fu-Sheng Guo

IPC分类号： H01L31/102 ,  H01L31/18

CPC分类号： H01L31/103 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/1464 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.

摘要翻译： 提供了一种用于减少感光二极管之间串扰的系统和方法。 在一个实施方案中，包含第一浓度的掺杂剂的隔离区位于感光二极管之间。 感光二极管具有小于掺杂剂的第一浓度的掺杂剂的第二浓度，这有助于防止光敏二极管扩散以形成感光二极管之间不期望的串扰的电势路径。

公开(公告)号：US08652868B2

公开(公告)日：2014-02-18

申请号：US13410165

申请日：2012-03-01

申请人： Yu-Shen Shih ,  Ching-Hwanq Su ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Kuo-Cheng Lee ,  Yen-Hsung Ho

发明人： Yu-Shen Shih ,  Ching-Hwanq Su ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Kuo-Cheng Lee ,  Yen-Hsung Ho

IPC分类号： H01L21/00

CPC分类号： H01L31/103 ,  H01L31/1804 ,  Y02E10/547

摘要： An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.

摘要翻译： 用于形成光电二极管的注入方法包括提供具有第一导电性的衬底，在衬底上生长外延层，从衬底的前侧在外延层中注入具有第二导电性的离子，并将第一导电性的离子注入 从衬底的前侧形成外延层以形成与前侧相邻的光有源区和在光有源区下面的光无源区。 通过采用注入方法，光有源区的平均掺杂密度约为光无源区的平均掺杂密度的十倍。

公开(公告)号：US08628998B2

公开(公告)日：2014-01-14

申请号：US13477897

申请日：2012-05-22

申请人： Yu-Ting Lin ,  Cheng-Jung Sung ,  Yu-Sheng Wang ,  Shiu-Ko JangJian ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Ching-Hwanq Su

发明人： Yu-Ting Lin ,  Cheng-Jung Sung ,  Yu-Sheng Wang ,  Shiu-Ko JangJian ,  Wei-Ming You ,  Chih-Cherng Jeng ,  Ching-Hwanq Su

IPC分类号： H01L21/00

CPC分类号： H01L27/14687 ,  H01L21/268 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689

摘要： A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.

摘要翻译： 一种方法包括在半导体衬底的背面进行研磨。 图像传感器设置在半导体衬底的前侧。 杂质掺杂到半导体衬底的背面的表面层中以形成掺杂层。 在掺杂层上进行多周期激光退火。

公开(公告)号：US20130193539A1

公开(公告)日：2013-08-01

申请号：US13429002

申请日：2012-03-23

申请人： Jung-Chi Jeng ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  Ching-Hwanq Su ,  Yan-Hua Lin ,  Yu-Shen Shih

发明人： Jung-Chi Jeng ,  Chih-Cherng Jeng ,  Chih-Kang Chao ,  Ching-Hwanq Su ,  Yan-Hua Lin ,  Yu-Shen Shih

IPC分类号： H01L31/0232 ,  H01L31/18

CPC分类号： H01L31/1804 ,  H01L27/1461 ,  H01L27/1464 ,  H01L27/14689 ,  H01L31/103 ,  Y02E10/547

摘要： A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

摘要翻译： 背面照明CMOS图像传感器包括使用第一高能离子注入工艺在衬底上形成的延伸的光有源区，以及使用第二高能离子注入工艺在衬底上形成的隔离区。 扩展的光有源区被隔离区包围，该隔离区具有与扩展的光活性区相同的深度。 扩展的光有源区域有助于增加转换成电子的光子数量，以提高量子效率。

公开(公告)号：US08049213B2

公开(公告)日：2011-11-01

申请号：US11958942

申请日：2007-12-18

申请人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

发明人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

IPC分类号： H01L21/66 ,  H01L23/544

CPC分类号： H01L22/14 ,  H01L22/12 ,  H01L22/20

摘要： A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

摘要翻译： 测量尺寸特性的方法包括提供衬底并在衬底上形成反射层。 然后在反射层上形成电介质层。 电介质层包括在透明区域内插入的光栅图案和电阻率测试线。 然后将辐射引导到电介质层上，使得一些辐射透过透明区域到达反射层。 然后从由金属光栅图案反射和散射的辐射中检测出辐射图。 分析辐射图以确定第一维信息。 然后测量电阻率测试线的电阻，并分析该电阻以确定第二维信息。 然后比较第一和第二维信息。

公开(公告)号：US20090152545A1

公开(公告)日：2009-06-18

申请号：US11958942

申请日：2007-12-18

申请人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

发明人： Ching-Chung Su ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Yih Song Chiu ,  Pin Chia Su ,  Chih-Cherng Jeng ,  Kuo-Hsiu Wei

IPC分类号： H01L23/58 ,  H01L21/66

CPC分类号： H01L22/14 ,  H01L22/12 ,  H01L22/20

摘要： A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test line inset in a transparent region. Radiation is then directed onto the dielectric layer so that some of the radiation is transmitted through the transparent region to the reflective layer. A radiation pattern is then detected from the radiation reflected and scattered by the metal grating pattern. The radiation pattern is analyzed to determine a first dimensional information. Then the resistance of the resistivity test line is measured, and that resistance is analyzed to determine a second dimensional information. The first and second dimensional informations are then compared.

摘要翻译： 测量尺寸特性的方法包括提供衬底并在衬底上形成反射层。 然后在反射层上形成电介质层。 电介质层包括在透明区域内插入的光栅图案和电阻率测试线。 然后将辐射引导到电介质层上，使得一些辐射透过透明区域到达反射层。 然后从由金属光栅图案反射和散射的辐射中检测出辐射图。 分析辐射图以确定第一维信息。 然后测量电阻率测试线的电阻，并分析该电阻以确定第二维信息。 然后比较第一和第二维信息。