公开(公告)号：US10403737B2

公开(公告)日：2019-09-03

申请号：US16193880

申请日：2018-11-16

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3115

摘要： A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.

公开(公告)号：US10164065B1

公开(公告)日：2018-12-25

申请号：US15629862

申请日：2017-06-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Chih-Yang Yeh ,  Jeng-Ya David Yeh

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423

摘要： In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface.

公开(公告)号：US11670697B2

公开(公告)日：2023-06-06

申请号：US17353606

申请日：2021-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/165 ,  H01L29/51

CPC分类号： H01L29/42372 ,  H01L21/28088 ,  H01L21/7684 ,  H01L21/76846 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53204 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/165 ,  H01L29/517 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor device includes a substrate comprising a semiconductor fin, a gate structure over the semiconductor fin, and source/drain structures over the semiconductor fin and on opposite sides of the gate structure. The gate stack comprises a high-k dielectric layer; a first work function metal layer over the high-k dielectric layer; an oxide of the first work function metal layer over the first work function metal layer; and a second work function metal layer over the oxide of the first work function metal layer, in which the first and second work function metal layers have different compositions; and a gate electrode over the second work function metal layer.

公开(公告)号：US11145730B2

公开(公告)日：2021-10-12

申请号：US16678642

申请日：2019-11-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Chih-Yang Yeh ,  Jeng-Ya David Yeh

IPC分类号： H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/51 ,  H01L29/417 ,  H01L29/43 ,  H01L29/78 ,  H01L29/165

摘要： A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

公开(公告)号：US11043567B2

公开(公告)日：2021-06-22

申请号：US16115390

申请日：2018-08-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Chih-Yang Yeh ,  Shu-Hui Wang ,  Jeng-Ya David Yeh

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L29/165 ,  H01L29/51

摘要： A semiconductor device includes a substrate, a gate stack. The substrate includes a semiconductor fin. The gate stack is disposed on the semiconductor fin. The gate stack includes a dielectric layer disposed over the semiconductor fin, and a metal stack disposed over the dielectric layer and having a first metallic layer and a second metallic layer over the first metallic layer, and a gate electrode disposed over the metal stack. The first metallic layer and the second metallic layer have a first element, and a percentage of the first element in the first metallic layer is greater than that in the second metallic layer.

公开(公告)号：US10529629B2

公开(公告)日：2020-01-07

申请号：US15966299

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US10134873B2

公开(公告)日：2018-11-20

申请号：US15355901

申请日：2016-11-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Chun-Sheng Liang ,  Shu-Hui Wang ,  Kuo-Hua Pan

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L29/51

摘要： A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.

公开(公告)号：US20230268404A1

公开(公告)日：2023-08-24

申请号：US18309564

申请日：2023-04-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Ming-Chia Tai ,  Ju-Yuan Tzeng ,  Hsin-Che Chiang ,  Yuan-Sheng Huang ,  Chun-Sheng Liang

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L21/3065 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L29/66795 ,  H01L21/3065 ,  H01L27/0886 ,  H01L21/823431 ,  H01L29/785

摘要： A method of applying and then removing a protective layer over a portion of a gate stack is provided. The protective layer is deposited and then a plasma precursor is separated into components. Neutral radicals are then utilized in order to remove the protective layer. In some embodiments the removal also forms a protective by-product which helps to protect underlying layers from damage during the etching process.

公开(公告)号：US20200152521A1

公开(公告)日：2020-05-14

申请号：US16735184

申请日：2020-01-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L27/092

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

公开(公告)号：US20190333826A1

公开(公告)日：2019-10-31

申请号：US15966299

申请日：2018-04-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ju-Li Huang ,  Hsin-Che Chiang ,  Ju-Yuan Tzeng ,  Wei-Ze Xu ,  Yueh-Yi Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311

摘要： A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.