公开(公告)号：US20180151412A1

公开(公告)日：2018-05-31

申请号：US15438883

申请日：2017-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Jung Huang ,  Hsu-Shui Liu ,  Han-Wen Liao ,  Yu-Yao Huang ,  Hsiao-Wei Chen ,  Yung-Lin Hsu ,  Kuang-Huan Hsu

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02112 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L29/0649 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

公开(公告)号：US12051593B2

公开(公告)日：2024-07-30

申请号：US18126861

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Li-Hsin Chu ,  Po-Feng Tsai ,  Henry Peng ,  Kuang Huan Hsu ,  Tsung Wei Chen ,  Yung-Lin Hsu

IPC: H01L21/265 ,  C23C14/48 ,  C23C14/54 ,  H01L21/66

CPC classification number: H01L21/26586 ,  C23C14/48 ,  C23C14/54 ,  H01L22/14

Abstract: The present disclosure describes a system and a method for an ion implantation (IMP) process. The system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.

公开(公告)号：US11626315B2

公开(公告)日：2023-04-11

申请号：US15438883

申请日：2017-02-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Jung Huang ,  Hsu-Shui Liu ,  Han-Wen Liao ,  Yu-Yao Huang ,  Hsiao-Wei Chen ,  Yung-Lin Hsu ,  Kuang-Huan Hsu

IPC: H01L21/3105 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78

Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

公开(公告)号：US20190164794A1

公开(公告)日：2019-05-30

申请号：US15904032

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Yung-Lin Hsu ,  Kuang Huan Hsu ,  Jeff Chen ,  Steven Huang ,  Yueh-Lun Yang

IPC: H01L21/677 ,  H01L21/67

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

公开(公告)号：US11587811B2

公开(公告)日：2023-02-21

申请号：US17317747

申请日：2021-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Yung-Lin Hsu ,  Kuang Huan Hsu ,  Jeff Chen ,  Steven Huang ,  Yueh-Lun Yang

IPC: H01L21/677 ,  H01L21/67

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

公开(公告)号：US11011401B2

公开(公告)日：2021-05-18

申请号：US15904032

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Yung-Lin Hsu ,  Kuang Huan Hsu ,  Jeff Chen ,  Steven Huang ,  Yueh-Lun Yang

IPC: H01L21/677 ,  H01L21/67

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

公开(公告)号：US09804098B2

公开(公告)日：2017-10-31

申请号：US14887339

申请日：2015-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang

IPC: G01N21/88 ,  G01N21/95

CPC classification number: G01N21/8851 ,  G01N21/9501 ,  G01N2021/8864

Abstract: A defect recognition system and a defect recognition method are described. The method includes inspecting a wafer to generate a defect map and locating at least one defect on the wafer by using the defect map; measuring at least one light component of light reflected from one of the at least one defect; comparing the at least one light component measured from the light reflected from the defect with a characteristic curve of the corresponding light component of the defect; and estimating an occurrence time of the defect based on the comparison.

公开(公告)号：US09719941B2

公开(公告)日：2017-08-01

申请号：US14941670

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang

IPC: G01N21/00 ,  G01N21/88 ,  G01N21/95

CPC classification number: G01N21/8851 ,  G01N21/94 ,  G01N21/9501 ,  G01N2021/8864 ,  G01N2021/8887

Abstract: A defect recognition system and a defect recognition method are described. The method includes inspecting a wafer to generate a defect map and locating at least one defect on the wafer by using the defect map; analyzing light reflected from one of the at least one defect to obtain a spectrum of the light; comparing a waveform of the obtained spectrum with a plurality of waveforms respectively in spectrums of different substances; and determining a composition of the defect based on the comparison.

公开(公告)号：US12272580B2

公开(公告)日：2025-04-08

申请号：US18403613

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Yung-Lin Hsu ,  Kuang Huan Hsu ,  Jeff Chen ,  Steven Huang ,  Yueh-Lun Yang

IPC: H01L21/677 ,  H01L21/67

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

公开(公告)号：US11901206B2

公开(公告)日：2024-02-13

申请号：US18104731

申请日：2023-02-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Jung Huang ,  Yung-Lin Hsu ,  Kuang Huan Hsu ,  Jeff Chen ,  Steven Huang ,  Yueh-Lun Yang

IPC: H01L21/677 ,  H01L21/67

CPC classification number: H01L21/67703 ,  H01L21/67196 ,  H01L21/67727

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.