公开(公告)号：US11776880B2

公开(公告)日：2023-10-03

申请号：US17073937

申请日：2020-10-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Horng Chang ,  Jie-Cheng Deng ,  Tin-Hao Kuo ,  Ying-Yu Chen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/48 ,  H01L21/563 ,  H01L23/3142 ,  H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/83 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/92125 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/83

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

公开(公告)号：US10510608B2

公开(公告)日：2019-12-17

申请号：US15061876

申请日：2016-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jie-Cheng Deng ,  Horng-Huei Tseng ,  Yi-Jen Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/033 ,  H01L21/32 ,  H01L27/088 ,  H01L21/84 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

公开(公告)号：US20210050281A1

公开(公告)日：2021-02-18

申请号：US17073937

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Horng Chang ,  Jie-Cheng Deng ,  Tin-Hao Kuo ,  Ying-Yu Chen

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.

公开(公告)号：US09947592B2

公开(公告)日：2018-04-17

申请号：US14941677

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie-Cheng Deng ,  Yi-Jen Chen ,  Horng-Huei Tseng

IPC: H01L21/8228 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L27/108 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/13067

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

公开(公告)号：US09601492B1

公开(公告)日：2017-03-21

申请号：US14941663

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie-Cheng Deng ,  Yi-Jen Chen ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/785

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The insulating wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.

公开(公告)号：US10510840B2

公开(公告)日：2019-12-17

申请号：US15628243

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie-Cheng Deng ,  Yi-Jen Chen ,  Chia-Yang Liao

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01H29/06 ,  H01L29/775 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/786

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

公开(公告)号：US20220172997A1

公开(公告)日：2022-06-02

申请号：US17650950

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie-Cheng Deng ,  Horng-Huei Tseng ,  Yi-Jen Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/033 ,  H01L21/32 ,  H01L27/088

Abstract: A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

公开(公告)号：US10943977B2

公开(公告)日：2021-03-09

申请号：US16710352

申请日：2019-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie-Cheng Deng ,  Yi-Jen Chen ,  Chia-Yang Liao

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/06 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/786

Abstract: A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

公开(公告)号：US20170141111A1

公开(公告)日：2017-05-18

申请号：US14941677

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie-Cheng Deng ,  Yi-Jen Chen ,  Horng-Huei Tseng

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/823821 ,  H01L21/823487 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/13067

Abstract: FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and a single spacer wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The single spacer wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.