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公开(公告)号:US20250087588A1
公开(公告)日:2025-03-13
申请号:US18506739
申请日:2023-11-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Monsen Liu , Shuo-Mao Chen , Hsien-Wei Chen , Shin-Puu Jeng
IPC: H01L23/538 , H01L21/48 , H01L23/28 , H01L25/00 , H01L25/065 , H10B80/00
Abstract: A method includes forming first conductive elements on and extending through a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on and extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming second conductive elements extending through the second composite layer.
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公开(公告)号:US11984668B2
公开(公告)日:2024-05-14
申请号:US17360242
申请日:2021-06-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Monsen Liu , Lai Wei Chih , Chung-Hao Tsai , Jeng-Shien Hsieh , En-Hsiang Yeh , Chuei-Tang Wang
CPC classification number: H01Q9/0407 , H01L24/19 , H01L24/97 , H01Q1/38 , H01L21/568 , H01L2223/6677 , H01L2224/12105 , H01L2224/8203 , H01L2224/9222 , H01L2924/18162
Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.
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公开(公告)号:US09767957B2
公开(公告)日:2017-09-19
申请号:US13964539
申请日:2013-08-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Monsen Liu , Chung-Hao Tsai , En-Hsiang Yeh , Chuei-Tang Wang , Chen-Hua Yu
IPC: H01F41/04 , H01F27/28 , H01L23/64 , H01L23/522 , H01L49/02 , H01L23/00 , H01R43/26 , H01R24/56 , H01R24/48 , H01R24/40 , H01L23/50 , H01F17/00
CPC classification number: H01F41/04 , H01F17/0006 , H01F27/2804 , H01F41/042 , H01F41/043 , H01F41/045 , H01F41/046 , H01F2027/2814 , H01L23/50 , H01L23/5227 , H01L23/645 , H01L24/29 , H01L28/10 , H01R24/40 , H01R24/48 , H01R24/56 , H01R43/26 , Y10T29/4902 , Y10T29/49073 , Y10T29/49158 , Y10T29/49165 , Y10T29/49169
Abstract: A method making a three-dimensional inductor, the method including: forming a plurality of vias in a substrate or a molding compound, wherein the vias are arranged with spacings among them; forming a metal layer having interconnects, wherein the interconnects of the metal layer connect the plurality of vias on one end of the vias; forming a plurality of wires to connect the plurality of vias on the other end of the vias to form the 3D inductor; and tuning one or more of the plurality of wires to adjust a physical configuration and inductance value of the 3D inductor.
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公开(公告)号:US20150042438A1
公开(公告)日:2015-02-12
申请号:US13964539
申请日:2013-08-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Monsen Liu , Chung-Hao Tsai , En-Hsiang Yeh , Chuei-Tang Wang , Chen-Hua Yu
CPC classification number: H01F41/04 , H01F17/0006 , H01F27/2804 , H01F41/042 , H01F41/043 , H01F41/045 , H01F41/046 , H01F2027/2814 , H01L23/50 , H01L23/5227 , H01L23/645 , H01L24/29 , H01L28/10 , H01R24/40 , H01R24/48 , H01R24/56 , H01R43/26 , Y10T29/4902 , Y10T29/49073 , Y10T29/49158 , Y10T29/49165 , Y10T29/49169
Abstract: A tunable three-dimensional (3D) inductor comprises a plurality of vias arranged with spacing among them, a plurality of interconnects in a metal layer, wherein the plurality of interconnects connect the plurality of vias on one end, and a plurality of tunable wires that connects to the plurality of vias on the other end to form the 3D inductor. The physical configuration and inductance value of the 3D inductor are adjustable by tuning the plurality of tunable wires during manufacturing process.
Abstract translation: 可调谐三维(3D)电感器包括在它们之间间隔布置的多个通孔,金属层中的多个互连,其中多个互连件在一端连接多个通孔,以及多个可调电线, 连接到另一端的多个通孔以形成3D电感器。 通过在制造过程中调谐多个可调电线,可以调整3D电感器的物理配置和电感值。
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公开(公告)号:US20210328347A1
公开(公告)日:2021-10-21
申请号:US17360242
申请日:2021-06-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Monsen Liu , Lai Wei Chih , Chung-Hao Tsai , Jeng-Shien Hsieh , En-Hsiang Yeh , Chuei-Tang Wang
Abstract: A device includes a patch antenna, which includes a feeding line, and a ground panel over the feeding line. The ground panel has an aperture therein. A low-k dielectric module is over and aligned to the aperture. A patch is over the low-k dielectric module.
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