公开(公告)号：US12261036B2

公开(公告)日：2025-03-25

申请号：US18358508

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US11935746B2

公开(公告)日：2024-03-19

申请号：US17341332

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yi Chang ,  Chunyao Wang

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/477 ,  H01L29/66

CPC classification number: H01L21/027 ,  H01L21/3086 ,  H01L21/477 ,  H01L29/66795

Abstract: As deposited, hard mask thin films have internal stress components which are an artifact of the material, thickness, deposition process of the mask layer as well as of the underlying materials and topography. This internal stress can cause distortion and twisting of the mask layer when it is patterned, especially when sub-micron critical dimensions are being patterned. A stress-compensating process is employed to reduce the impact of this internal stress. Heat treatment can be employed to relax the stress, as an example. In another example, a second mask layer with an opposite internal stress component is employed to offset the internal stress component in the hard mask layer.

公开(公告)号：US20220029011A1

公开(公告)日：2022-01-27

申请号：US17157330

申请日：2021-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US10483168B2

公开(公告)日：2019-11-19

申请号：US15833912

申请日：2017-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

公开(公告)号：US20190148239A1

公开(公告)日：2019-05-16

申请号：US16203814

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

公开(公告)号：US12266728B2

公开(公告)日：2025-04-01

申请号：US18591730

申请日：2024-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Yu-Cheng Shiau ,  Chunyao Wang ,  Chih-Tang Peng ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/51 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

公开(公告)号：US20250048726A1

公开(公告)日：2025-02-06

申请号：US18927431

申请日：2024-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yi Kao ,  Hung Cheng Lin ,  Chunyao Wang ,  Yung-Cheng Lu ,  Chi On Chui

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

公开(公告)号：US20240379346A1

公开(公告)日：2024-11-14

申请号：US18783614

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US20230386826A1

公开(公告)日：2023-11-30

申请号：US18358508

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L21/0217 ,  H01L21/76224 ,  H01L21/0337 ,  H01L21/02208 ,  H01L21/3086 ,  H01L21/0228 ,  H01L29/66795 ,  H01L21/3081 ,  H01L29/66545 ,  H01L21/823431 ,  H01L29/785

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.

公开(公告)号：US11830727B2

公开(公告)日：2023-11-28

申请号：US17809917

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Che Hsieh ,  Ching Yu Huang ,  Hsin-Hao Yeh ,  Chunyao Wang ,  Tze-Liang Lee

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0217 ,  H01L21/0228 ,  H01L21/02208 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes placing a wafer into a process chamber, and depositing a silicon nitride layer on a base layer of the wafer. The process of depositing the silicon nitride layer includes introducing a silicon-containing precursor into the process chamber, purging the silicon-containing precursor from the process chamber, introducing hydrogen radicals into the process chamber, purging the hydrogen radicals from the process chamber; introducing a nitrogen-containing precursor into the process chamber, and purging the nitrogen-containing precursor from the process chamber.