公开(公告)号：US20240290662A1

公开(公告)日：2024-08-29

申请号：US18403056

申请日：2024-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yao-Teng CHUANG ,  Te-Yang LAI ,  Kuei-Lun LIN ,  Tsung-Da LIN ,  Chi On CHUI

IPC分类号： H01L21/8238 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L21/823857 ,  H01L21/3115 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

摘要： Dipole engineering techniques for stacked device structures are disclosed herein. According to various aspects of the present disclosure, an exemplary dipole engineering technique includes (1) forming at least two patterned dipole dopant source layers having different patterns and covering gate dielectric layers of some transistors, but not other transistors, (2) performing a thermal drive-in process (e.g., a dipole drive-in anneal), and (3) after removing the dipole dopant source layer, forming gate electrodes for the transistors, where a same gate electrode material is used for the transistors. Thickness(es) and/or material characteristics (e.g., dipole dopant) of the patterned dipole dopant source layers and/or parameters of the thermal drive-in process may be configured to achieve desired threshold voltages. Such technique may provide 2N threshold voltages (Vt), where N is a number of patterned dipole dopant source layers formed on the gate dielectric layers of the transistors to tune their threshold voltages.

公开(公告)号：US20240250153A1

公开(公告)日：2024-07-25

申请号：US18099405

申请日：2023-01-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kun-Yi LIN ,  Tai-Jung KUO ,  Yunn-Shiuan LIU ,  Zhen-Cheng WU ,  Chi On CHUI

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/4232 ,  H01L29/7851

摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a gate electrode disposed over a semiconductor substrate and a gate cut-fill structure disposed in the gate electrode to separate the gate electrode into two portions. The gate cut-fill structure includes a first liner, a second liner disposed on the first liner, and a dielectric material disposed on the second liner. The dielectric material has a “V” shaped cross-section.

公开(公告)号：US20230275143A1

公开(公告)日：2023-08-31

申请号：US18315204

申请日：2023-05-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsin-Yi LEE ,  Cheng-Lung HUNG ,  Chi On CHUI

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/6681 ,  H01L29/66545 ,  H01L21/823431 ,  H01L29/7851 ,  H01L29/0669

摘要： A method of forming a semiconductor device including forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, etching the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a work function metal layer surrounding each of the nanosheets, and depositing a fill metal layer over the work function metal layer without using a fluorine-containing precursor.

公开(公告)号：US20230274938A1

公开(公告)日：2023-08-31

申请号：US17837848

申请日：2022-06-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hao-Ming TANG ,  Shu-Han CHEN ,  Yun-San CHIEN ,  Da-Yuan LEE ,  Chi On CHUI ,  Tsung-Ju CHEN ,  Yi-Hsin TING ,  Han-Shen WANG

IPC分类号： H01L21/28 ,  H01L27/092 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L21/28202 ,  H01L27/0924 ,  H01L29/518 ,  H01L29/7851 ,  H01L29/66795 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878

摘要： In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.

公开(公告)号：US20240170485A1

公开(公告)日：2024-05-23

申请号：US18429734

申请日：2024-02-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kun-Yu LEE ,  Chun-Yao WANG ,  Chi On CHUI

IPC分类号： H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/02164 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7851

摘要： A semiconductor device includes a substrate, a pair of semiconductor fins, a dummy fin structure, a gate structure, a plurality of source/drain structures, a crystalline hard mask layer, and an amorphous hard mask layer. The pair of semiconductor fins extend upwardly from the substrate. The dummy fin structure extends upwardly above the substrate and is laterally between the pair of semiconductor fins. The gate structure extends across the pair of semiconductor fins and the dummy fin structure. The source/drain structures are above the pair of semiconductor fins and on either side of the gate structure. The crystalline hard mask layer extends upwardly from the dummy fin and has a U-shaped cross section. The amorphous hard mask layer is in the first hard mask layer, wherein the amorphous hard mask layer having an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

公开(公告)号：US20240145569A1

公开(公告)日：2024-05-02

申请号：US18404299

申请日：2024-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC分类号： H01L29/45 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/7851 ,  H01L21/823807 ,  H01L29/456 ,  H01L2029/7858

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

公开(公告)号：US20240128364A1

公开(公告)日：2024-04-18

申请号：US18190691

申请日：2023-03-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun-Ming LUNG ,  Chung-Ting KO ,  Ting-Hsiang CHANG ,  Sung-En LIN ,  Chi On CHUI

IPC分类号： H01L29/775 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/775 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439

摘要： A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.

公开(公告)号：US20240030354A1

公开(公告)日：2024-01-25

申请号：US18474842

申请日：2023-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Ru LIN ,  Shu-Han CHEN ,  Yi-Shao LI ,  Chun-Heng CHEN ,  Chi On CHUI

IPC分类号： H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02

CPC分类号： H01L29/78696 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/3065 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L21/0259

摘要： A device includes a first channel layer, a second channel layer, a gate structure, a source/drain epitaxial structure, and a source/drain contact. The first channel layer and the second channel layer are arranged above the first channel layer in a spaced apart manner over a substrate. The gate structure surrounds the first and second channel layers. The source/drain epitaxial structure is connected to the first and second channel layers. The source/drain contact is connected to the source/drain epitaxial structure. The second channel layer is closer to the source/drain contact than the first channel layer is to the source/drain contact, and the first channel layer is thicker than the second channel layer.

公开(公告)号：US20230065708A1

公开(公告)日：2023-03-02

申请号：US17461608

申请日：2021-08-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chung-Ting KO ,  Sung-En LIN ,  Chi On CHUI

IPC分类号： H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786

摘要： A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a substrate; forming an isolation feature adjacent semiconductor fin; recessing the isolation feature to form a recess; forming a metal-containing compound mask in the recess; depositing a stress layer over the metal-containing compound mask, such that the stress layer is in contact with a top surface of the metal-containing compound mask; and annealing the metal-containing compound mask when the stress layer is in contact with the top surface of the metal-containing compound mask.

公开(公告)号：US20210313438A1

公开(公告)日：2021-10-07

申请号：US17353460

申请日：2021-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yee-Chia YEO ,  Sung-Li WANG ,  Chi On CHUI ,  Jyh-Cherng SHEU ,  Hung-Li CHIANG ,  I-Sheng CHEN

IPC分类号： H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.