公开(公告)号：US20240395772A1

公开(公告)日：2024-11-28

申请号：US18324989

申请日：2023-05-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hsuan Tsai ,  Chin-Chuan Chang ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/40 ,  H01L23/498 ,  H01L23/538 ,  H01L29/66

Abstract: A package structure including a wiring substrate, semiconductor dies, and a dielectric layer is provided. The wiring substrate includes die bonding regions and guiding patterns (auxiliary patterns, or dummy patterns) distributed between the die bonding regions. The semiconductor dies are disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies. The dielectric layer is disposed the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns.

公开(公告)号：US20230197653A1

公开(公告)日：2023-06-22

申请号：US18172326

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Szu-Wei Lu ,  Kun-Tong Tsai ,  Hung-Chih Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L21/568 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/06517

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

公开(公告)号：US11205579B2

公开(公告)日：2021-12-21

申请号：US15620590

申请日：2017-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu-Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US20210217671A1

公开(公告)日：2021-07-15

申请号：US17214921

申请日：2021-03-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Szu-Wei Lu

IPC: H01L21/66 ,  H01L21/56 ,  H01L21/306

Abstract: An apparatus for detecting an endpoint of a grinding process includes a connecting device, a timer and a controller. The connecting device is connected to a sensor that periodically senses an interface of a reconstructed wafer comprising a plurality of dies of at least two types to generate a thickness signal comprising thicknesses from a surface of an insulating layer of the reconstructed wafer to the interface of the reconstructed wafer. The timer is configured to generate a clock signal having a plurality of pulses with a time interval. The controller is coupled to the sensor and the timer, and configured to filter the thickness signal according to the clock signal to output a thickness extremum among the thicknesses in the thickness signal within each time interval, wherein the thickness signal after the filtering is used to determine the endpoint of the grinding process being performed on the reconstructed wafer.

公开(公告)号：US20170278723A1

公开(公告)日：2017-09-28

申请号：US15620590

申请日：2017-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu-Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/56 ,  B29C33/12 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US09406598B2

公开(公告)日：2016-08-02

申请号：US14319678

申请日：2014-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L29/40 ,  H01L23/498 ,  H01L23/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/48 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.

Abstract translation: 一个实施方案是包括半导体管芯，半导体管芯的第一侧上的粘合剂层和围绕半导体管芯和粘合剂层的模制化合物的器件，其中模塑料与粘合剂层处于相同的水平。 该器件还包括电耦合到半导体管芯的第二侧的第一钝化后互连（PPI）和电耦合到第一PPI的第一连接器，其中第一连接器在模制化合物上方并对齐。

公开(公告)号：US20140210080A1

公开(公告)日：2014-07-31

申请号：US13753204

申请日：2013-01-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chin-Chuan Chang ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Wan-Ting Shih

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/49816 ,  H01L21/50 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/538 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/73 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/117 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/80001 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.

Abstract translation: 形成PoP器件的方法包括将粘合剂层放置在载体衬底上，将多个芯片封装耦合到载体衬底上的粘合剂层，将结合层放置在芯片封装上，以及将多个芯片耦合到键合 层上的芯片封装。 该方法还包括注射模塑料以将芯片封装和芯片封装在载体衬底上，研磨模塑料以暴露芯片的多个连接元件和芯片封装的多个第二连接元件，从而形成再分配 层（RDL）和暴露的连接元件和第二连接元件，在RDL上形成球栅阵列（BGA），并且使载体基板去粘合。

公开(公告)号：US08785299B2

公开(公告)日：2014-07-22

申请号：US13691536

申请日：2012-11-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L21/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3192 ,  H01L23/48 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An embodiment is a device comprising a semiconductor die, an adhesive layer on a first side of the semiconductor die, and a molding compound surrounding the semiconductor die and the adhesive layer, wherein the molding compound is at a same level as the adhesive layer. The device further comprises a first post-passivation interconnect (PPI) electrically coupled to a second side of the semiconductor die, and a first connector electrically coupled to the first PPI, wherein the first connector is over and aligned to the molding compound.

Abstract translation: 一个实施方案是包括半导体管芯，半导体管芯的第一侧上的粘合剂层和围绕半导体管芯和粘合剂层的模制化合物的器件，其中模塑料与粘合剂层处于相同的水平。 该器件还包括电耦合到半导体管芯的第二侧的第一钝化后互连（PPI）和电耦合到第一PPI的第一连接器，其中第一连接器在模制化合物上方并对齐。

公开(公告)号：US12074112B2

公开(公告)日：2024-08-27

申请号：US18307114

申请日：2023-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Chuan Chang ,  Szu-Wei Lu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: A package structure is provided. The package structure includes a first redistribution structure and an interposer over the first redistribution structure. The interposer includes a through via electrically connected to the first redistribution structure and a conductive pillar over the through via. The package structure also includes a first molding compound layer surrounding the interposer. The package structure further includes a second redistribution structure over the first molding compound layer and electrically connected to the conductive pillar. The package structure also includes a semiconductor die over and electrically connected to the second redistribution structure.

公开(公告)号：US20240274560A1

公开(公告)日：2024-08-15

申请号：US18641442

申请日：2024-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Chao Mao ,  Chin-Chuan Chang ,  Szu-Wei Lu ,  Kun-Tong Tsai ,  Hung-Chih Chen

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/06517 ,  H01L2224/214

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.