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公开(公告)号：US20230063518A1
公开(公告)日：2023-03-02
申请号：US17460768
申请日：2021-08-30
发明人： Shao-Chun CHIU , Wen-Feng LIAO , Hao CHEN , Chun-Hsing CHEN
IPC分类号： G01R1/04
摘要： A testing device for testing an integrated circuit package is provided, including a printed circuit board having a first surface, a second surface, and multiple conductive layers between the first and second surfaces. A metal layer is formed on the second surface and is electrically connected to one of the conductive layers that is grounded. A testing socket is disposed over the first surface. A conductive fastener secures the testing socket to the printed circuit board and is electrically connected to the metal layer. A cover is disposed over the testing socket to form a space for accommodating the integrated circuit package between the cover and the testing socket. The cover has a conductive surface in contact with the integrated circuit package. A conductive element assembly is disposed between the cover and the testing socket and is electrically connected to the conductive surface and the conductive fastener.
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公开(公告)号：US20220283221A1
公开(公告)日：2022-09-08
申请号：US17751640
申请日：2022-05-23
发明人： Mill-Jer WANG , Kuo-Chuan LIU , Ching-Nen PENG , Hung-Chih LIN , Hao CHEN
IPC分类号： G01R31/28 , G01R31/3185 , G01R1/04 , G01R1/067
摘要： A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
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3.发明申请公开(公告)号：US20150323589A1
公开(公告)日：2015-11-12
申请号：US14804319
申请日：2015-07-20
发明人： Min-Jer Wang , Ching-Nen PENG , Chewn-Pu JOU , Feng Wei KUO , Hao CHEN , Hung-Chih LIN , Huan-Neng CHEN , Kuang-Kai YEN , Ming-Chieh LIU , Tsung-Hsiung LEE
IPC分类号： G01R31/28 , H01L23/538 , H02J5/00 , H01L25/065
CPC分类号： H02J50/40 , G01R31/2856 , G01R31/2884 , G01R31/2889 , G01R31/3025 , G06F17/5068 , H01L23/538 , H01L23/544 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2223/54446 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/81193 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311 , H02J5/005 , H02J50/10 , H02J50/20 , H02J50/80 , H01L2224/81
摘要： A composite integrated circuit (IC) includes a first circuit layer, a second circuit layer having a first chip and a second chip, and a first wireless power transfer (WPT) device in the first chip or the first circuit layer. The first WPT device generates a power supply voltage by extracting energy from an electromagnetic signal. A first tracking circuit in the second chip or the first circuit layer is powered by the power supply voltage from the first WPT device and stores or outputs tracking data in response to an instruction extracted from the electromagnetic signal.
摘要翻译： 复合集成电路（IC）包括第一电路层，具有第一芯片和第二芯片的第二电路层以及第一芯片或第一电路层中的第一无线电力传输（WPT）装置。 第一WPT装置通过从电磁信号中提取能量来产生电源电压。 第二芯片或第一电路层中的第一跟踪电路由来自第一WPT设备的电源电压供电，并响应于从电磁信号提取的指令存储或输出跟踪数据。
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公开(公告)号：US20150130498A1
公开(公告)日：2015-05-14
申请号：US14601671
申请日：2015-01-21
发明人： Mill-Jer WANG , Ching-Nen PENG , Hung-Chih LIN , Hao CHEN
CPC分类号： G01R1/07307 , G01R31/11 , G01R31/2601 , G01R31/2891 , G01R31/3191 , G01R35/005
摘要： A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board.
摘要翻译： 晶片探测系统包括连接到测试头的多个接触引脚。 该系统还包括与测试头电连接的探针卡，其中探针卡包括在电路板的相对侧上具有多个接触垫的电路板。
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5.发明申请METHOD OF TESTING THROUGH SILICON VIAS (TSVS) OF THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) 有权通过三维集成电路（3DIC）测量硅VI（TSVS）的方法公开(公告)号：US20130196458A1
公开(公告)日：2013-08-01
申请号：US13800626
申请日：2013-03-13
发明人： Hung-Chih LIN , Mill-Jer WANG , Ching-Nen PENG , Hao CHEN
IPC分类号： H01L21/66
CPC分类号： H01L22/14 , H01L22/32 , H01L22/34 , H01L24/02 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0237 , H01L2224/02372 , H01L2224/0401 , H01L2224/13025 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16155 , H01L2224/16225 , H01L2224/81193 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06596 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.
摘要翻译： 在通过衬底上的互连测试多个通过硅通孔（TSV）连接在一起的方法中，将测试信号施加到多个测试焊盘中的第一测试焊盘，并且在第二测试焊盘处测量返回信号 在多个测试焊盘之间。 多个测试焊盘中的至少一个测试焊盘接地到基板。 多个测试焊盘的剩余测试焊盘或者连接到多个链接的TSV或接地。
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公开(公告)号：US20230065443A1
公开(公告)日：2023-03-02
申请号：US17460803
申请日：2021-08-30
发明人： Wen-Yi LIN , Hao CHEN , Chuan-Hsiang SUN , Mill-Jer WANG , Chien-Chen LI , Chen-Shien CHEN
IPC分类号： G01R1/067
摘要： A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The first probe pillar has a first protruding portion protruding from the bottom surface. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The redistribution structure is in direct contact with the flexible substrate and the first probe pillar. The redistribution structure includes a dielectric structure and a wiring structure in the dielectric structure. The wiring structure is electrically connected to the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.
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公开(公告)号：US20170242071A1
公开(公告)日：2017-08-24
申请号：US15589435
申请日：2017-05-08
发明人： Min-Jer WANG , Ching-Nen PENG , Chewn-Pu JOU , Feng Wei KUO , Hao CHEN , Hung-Chih LIN , Huan-Neng CHEN , Kuang-Kai YEN , Ming-Chieh LIU , Tsung-Hsiung LEE
IPC分类号： G01R31/302 , H01L25/065 , G01R31/28 , H02J50/20
CPC分类号： H02J50/40 , G01R31/2856 , G01R31/2884 , G01R31/2889 , G01R31/3025 , G06F17/5068 , H01L23/538 , H01L23/544 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2223/54446 , H01L2224/14181 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/81193 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311 , H02J5/005 , H02J50/10 , H02J50/20 , H02J50/80 , H01L2224/81 , H01L2224/1403
摘要： An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
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