公开(公告)号：US20150130498A1

公开(公告)日：2015-05-14

申请号：US14601671

申请日：2015-01-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mill-Jer WANG ,  Ching-Nen PENG ,  Hung-Chih LIN ,  Hao CHEN

IPC分类号： G01R1/073 ,  G01R31/26

CPC分类号： G01R1/07307 ,  G01R31/11 ,  G01R31/2601 ,  G01R31/2891 ,  G01R31/3191 ,  G01R35/005

摘要： A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board.

摘要翻译： 晶片探测系统包括连接到测试头的多个接触引脚。 该系统还包括与测试头电连接的探针卡，其中探针卡包括在电路板的相对侧上具有多个接触垫的电路板。

公开(公告)号：US20130196458A1

公开(公告)日：2013-08-01

申请号：US13800626

申请日：2013-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Chih LIN ,  Mill-Jer WANG ,  Ching-Nen PENG ,  Hao CHEN

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  H01L22/32 ,  H01L22/34 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0237 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00

摘要： In a method of testing a plurality of through silicon vias (TSVs) chained together by interconnect on a substrate, a test signal is applied to a first test pad among a plurality of test pads, and a return signal is measured at a second test pad among the plurality of test pads. At least one test pad of the plurality of test pads is grounded to the substrate. The remaining test pads of the plurality of test pads are either connected to the plurality of chained TSVs or are grounded.

摘要翻译： 在通过衬底上的互连测试多个通过硅通孔（TSV）连接在一起的方法中，将测试信号施加到多个测试焊盘中的第一测试焊盘，并且在第二测试焊盘处测量返回信号 在多个测试焊盘之间。 多个测试焊盘中的至少一个测试焊盘接地到基板。 多个测试焊盘的剩余测试焊盘或者连接到多个链接的TSV或接地。

公开(公告)号：US20220283221A1

公开(公告)日：2022-09-08

申请号：US17751640

申请日：2022-05-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Mill-Jer WANG ,  Kuo-Chuan LIU ,  Ching-Nen PENG ,  Hung-Chih LIN ,  Hao CHEN

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R1/04 ,  G01R1/067

摘要： A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

公开(公告)号：US20210280477A1

公开(公告)日：2021-09-09

申请号：US17328801

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mill-Jer WANG ,  Tang-Jung CHIU ,  Chi-Chang LAI ,  Chia-Heng TSAI ,  Mirng-Ji LII ,  Weii LIAO

IPC分类号： H01L21/66 ,  H01L23/552 ,  H01L27/01

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.

公开(公告)号：US20230065443A1

公开(公告)日：2023-03-02

申请号：US17460803

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wen-Yi LIN ,  Hao CHEN ,  Chuan-Hsiang SUN ,  Mill-Jer WANG ,  Chien-Chen LI ,  Chen-Shien CHEN

IPC分类号： G01R1/067

摘要： A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The first probe pillar has a first protruding portion protruding from the bottom surface. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The redistribution structure is in direct contact with the flexible substrate and the first probe pillar. The redistribution structure includes a dielectric structure and a wiring structure in the dielectric structure. The wiring structure is electrically connected to the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.

公开(公告)号：US20140354322A1

公开(公告)日：2014-12-04

申请号：US14459801

申请日：2014-08-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Sandeep Kumar GOEL ,  Mill-Jer WANG

IPC分类号： G01R31/28 ,  G01R1/073 ,  G01R1/04

CPC分类号： G01R31/2889 ,  G01R1/0408 ,  G01R1/07342 ,  G01R31/31908

摘要： A method of testing an integrated circuit die comprises partitioning a first probe card partition layout of the integrated circuit die having one or more sections comprising a first quantity of section types into a second probe card partition layout having a greater quantity of sections comprising a second quantity of section types, the second quantity of section types being less than the first quantity of section types. The method also comprises using one or more probe cards to test the sections in the second probe card partition layout, each of the one or more probe cards having a test contact pattern that corresponds with a test contact pattern of one of each section type included in the second probe card partition layout.

摘要翻译： 一种测试集成电路管芯的方法包括将具有一个或多个部分的集成电路管芯的第一探针卡分隔布局分成包括第一数量的部分类型到具有更大数量的部分的第二探针卡分配布局，所述部分包括第二数量 的截面类型，第二数量的截面类型小于第一数量的截面类型。 该方法还包括使用一个或多个探针卡来测试第二探针卡分区布局中的部分，所述一个或多个探针卡中的每一个具有与包括在每个部分类型之一的测试接触图案相对应的测试接触图案 第二个探针卡分区布局。