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    COMMUNICATION SYSTEM AND METHOD OF DATA COMMUNICATIONS
    2.
    发明申请
    COMMUNICATION SYSTEM AND METHOD OF DATA COMMUNICATIONS 审中-公开

    公开(公告)号：US20200162125A1

    公开(公告)日：2020-05-21

    申请号：US16773448

    申请日：2020-01-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Feng Wei KUO ,  William Wu SHEN ,  Chewn-Pu JOU ,  Huan-Neng CHEN ,  Lan-Chou CHO

    IPC: H04B3/04 ,  H03H7/01 ,  H03G5/28 ,  H04L27/22 ,  H03G3/30 ,  H03H11/04 ,  H04L27/38

    Abstract: A communication system includes a modulator configured to generate a modulated signal responsive to at least a data signal, and a demodulator configured to demodulate the modulated signal responsive to a first carrier signal. The demodulator includes a filter configured to generate a filtered first signal based on a first signal, and a gain adjusting circuit coupled to the filter. The first signal is based on the first carrier signal and modulated signal. The filter has a gain controlled by a set of control signals. The gain adjusting circuit is configured to adjust the gain of the filter, and to generate the set of control signals based on a voltage of the filtered first signal and a voltage of the first signal. The gain adjusting circuit includes a first peak detector coupled to the filter, and configured to detect a peak value of the voltage of the filtered first signal.

    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE
    5.
    发明申请
    AUTO FREQUENCY CALIBRATION FOR A PHASE LOCKED LOOP AND METHOD OF USE 有权
    用于相位锁定环的自动频率校准及其使用方法

    公开(公告)号：US20150130518A1

    公开(公告)日：2015-05-14

    申请号：US14603900

    申请日：2015-01-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Yen-Jen CHEN ,  Feng Wei KUO ,  Huan-Neng CHEN ,  Chewn-Pu JOU

    IPC: H03L7/08 ,  H03M1/00 ,  G04F10/00 ,  H03L7/099 ,  H03L7/085

    CPC classification number: H03L7/0802 ,  G04F10/005 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0992 ,  H03L7/101 ,  H03L7/103 ,  H03L7/104 ,  H03L7/1976 ,  H03L2207/50 ,  H03M1/002 ,  H03M3/32

    Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

    Abstract translation: 一种装置，包括代码发生器，其被配置为基于参考频率和相位差信号产生粗调谐信号和复位信号。 该装置还包括数字环路滤波器，其配置为基于相位差信号产生微调信号。 该装置还包括电压控制振荡器，被配置为基于粗调谐信号和微调信号产生输出信号。 该装置还包括分配器，其被配置为基于分频器控制信号和输出信号产生分频器频率。 相位差信号至少部分地基于分频器，并且分频器被配置为基于复位信号被复位。

    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER
    6.
    发明申请
    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER AND FREQUENCY DIVIDER 有权
    分离环路滤波器和频率分路器的相位锁定

    公开(公告)号：US20140333355A1

    公开(公告)日：2014-11-13

    申请号：US14444385

    申请日：2014-07-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Feng Wei KUO ,  Shyh-An CHI ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

    IPC: H03L7/07 ,  H03L7/099 ,  H03L7/093

    CPC classification number: H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

    Abstract: A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.

    Abstract translation: 共享环路滤波器包括被配置为选择性地接收来自第一电荷泵的第一输入的输入端口。 第一电荷泵连接到第一芯片中的第一锁相环（PLL）。 所述输入端口还被配置为选择性地从第二电荷泵接收第二输入，所述第二电荷泵连接到与所述第一裸片分开的第二模具中的第二PLL。 共享环路滤波器还包括被配置为选择性地向第一压控振荡器（VCO）提供输出的输出端口。 第一个VCO连接到第一个PLL。 输出端口还被配置为选择性地将第二输出输出到第二VCO。 第二个VCO连接到第二个PLL。

    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER
    7.
    发明申请
    PHASE-LOCKED LOOPS THAT SHARE A LOOP FILTER 有权
    分离循环过滤器的相位锁定

    公开(公告)号：US20140015576A1

    公开(公告)日：2014-01-16

    申请号：US14025125

    申请日：2013-09-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Feng Wei KUO ,  Shyh-An CHI ,  Huan-Neng CHEN ,  Yen-Jen CHEN ,  Chewn-Pu JOU

    IPC: H03L7/06

    CPC classification number: H03L7/07 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099

    Abstract: An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.

    Abstract translation: 集成电路包括第一管芯和第二管芯。 第一管芯包括第一锁相环（PLL），第二管芯包括第二PLL。 集成电路包括共享环路滤波器，其中第一管芯中的第一PLL与共享环路滤波器组合以形成第一PLL反馈环路，第二管芯中的第二PLL与共享环路滤波器组合以形成第二PLL PLL反馈环路和共享环路滤波器被配置为向第一PLL反馈环路和第二PLL反馈环路中的每一个提供可配置带宽。

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