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公开(公告)号：US20240203936A1
公开(公告)日：2024-06-20
申请号：US18592523
申请日：2024-03-01
Inventor： Mao-Yen Chang , Yu-Chia Lai , Cheng-Shiuan Wong , Ting Hao Kuo , Ching-Hua Hsieh , Hao-Yi Tsai , Kuo-Lung Pan , Hsiu-Jen Lin
IPC: H01L23/00 , H01L21/56 , H01L23/544 , H01L23/58
CPC classification number: H01L24/96 , H01L21/561 , H01L21/568 , H01L23/544 , H01L23/562 , H01L23/585 , H01L24/24 , H01L24/82 , H01L24/73 , H01L2223/5442 , H01L2223/54426 , H01L2224/24137 , H01L2224/24146 , H01L2224/24265 , H01L2224/73204 , H01L2224/73209 , H01L2224/73217 , H01L2224/82005 , H01L2224/82947
Abstract: A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.
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公开(公告)号：US20210305212A1
公开(公告)日：2021-09-30
申请号：US17315381
申请日：2021-05-10
Inventor： Wei-Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo-Lung Pan , Ting Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC: H01L25/065 , H01L23/00 , H01L25/00
Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
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公开(公告)号：US20230068263A1
公开(公告)日：2023-03-02
申请号：US17460319
申请日：2021-08-30
Inventor： Mao-Yen Chang , Yu-Chia Lai , Cheng-Shiuan Wong , Ting Hao Kuo , Ching-Hua Hsieh , Hao-Yi Tsai , Kuo-Lung Pan , Hsiu-Jen Lin
IPC: H01L23/00 , H01L21/56 , H01L23/58 , H01L23/544
Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
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4.发明公开公开(公告)号：US20240153821A1
公开(公告)日：2024-05-09
申请号：US18173086
申请日：2023-02-23
Inventor： Chen-Shien CHEN , Chi-Yen Lin , Hsu-Hsien Chen , Ting Hao Kuo , Chang-Ching Lin
CPC classification number: H01L21/78 , H01L23/564 , H10B80/00 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/80 , H01L2224/0557 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05657 , H01L2224/05684 , H01L2224/06181 , H01L2224/08145 , H01L2224/80006 , H01L2224/80357 , H01L2224/80379 , H01L2224/80895 , H01L2224/80896 , H01L2924/0504 , H01L2924/0544 , H01L2924/10156 , H01L2924/1431 , H01L2924/14361
Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.
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公开(公告)号：US11942451B2
公开(公告)日：2024-03-26
申请号：US17460319
申请日：2021-08-30
Inventor： Mao-Yen Chang , Yu-Chia Lai , Cheng-Shiuan Wong , Ting Hao Kuo , Ching-Hua Hsieh , Hao-Yi Tsai , Kuo-Lung Pan , Hsiu-Jen Lin
IPC: H01L21/56 , H01L23/00 , H01L23/544 , H01L23/58
CPC classification number: H01L24/96 , H01L21/561 , H01L21/568 , H01L23/544 , H01L23/562 , H01L23/585 , H01L24/24 , H01L24/82 , H01L24/73 , H01L2223/5442 , H01L2223/54426 , H01L2224/24137 , H01L2224/24146 , H01L2224/24265 , H01L2224/73204 , H01L2224/73209 , H01L2224/73217 , H01L2224/82005 , H01L2224/82947
Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.
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Patent Agency Ranking
公开(公告)号：US20230223382A1
公开(公告)日：2023-07-13
申请号：US18185358
申请日：2023-03-16
Inventor： Wei-Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo-Lung Pan , Ting Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC: H01L25/065 , H01L23/31 , H01L23/538 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L23/3128 , H01L23/5383 , H01L24/16 , H01L25/50 , H01L2224/16225 , H01L2224/32145 , H01L24/32 , H01L2224/73253 , H01L24/73 , H01L2224/73203
Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.
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公开(公告)号：US20220415737A1
公开(公告)日：2022-12-29
申请号：US17358001
申请日：2021-06-25
Inventor： Cheng-Chieh Wu , Ting Hao Kuo , Kuo-Lung Pan , Po-Yuan Teng , Yu-Chia Lai , Shu-Rong Chun , Mao-Yen Chang , Wei-Kang Hsieh , Pavithra Sriram , Hao-Yi Tsai , Po-Han Wang , Yu-Hsiang Hu , Hung-Jui Kuo
IPC: H01L23/31 , H01L23/538 , H01L23/29 , H01L25/065 , H01L23/00 , H01L21/56 , H01L21/48
Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.
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公开(公告)号：US12166015B2
公开(公告)日：2024-12-10
申请号：US18185358
申请日：2023-03-16
Inventor： Wei-Kang Hsieh , Hung-Yi Kuo , Hao-Yi Tsai , Kuo-Lung Pan , Ting Hao Kuo , Yu-Chia Lai , Mao-Yen Chang , Po-Yuan Teng , Shu-Rong Chun
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/00
Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.
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公开(公告)号：US20230260915A1
公开(公告)日：2023-08-17
申请号：US18303589
申请日：2023-04-20
Inventor： Hao-Yi Tsai , Tzuan-Horng Liu , Ting Hao Kuo
IPC: H01L23/538 , H01L23/00 , H01L23/31 , H01L23/48 , H01L25/065
CPC classification number: H01L23/5381 , H01L24/08 , H01L23/3107 , H01L23/481 , H01L25/0655 , H01L24/24 , H01L2224/24225 , H01L2224/08145
Abstract: A semiconductor structure includes a first die, a first encapsulant, a second die and a second encapsulant. The first die includes a first dielectric layer and first conductive pads in the first dielectric layer. The first encapsulant laterally encapsulates and is in direct contact with the first dielectric layer of the first die. The second die includes a second dielectric layer and second conductive pads in the second dielectric layer. The second encapsulant laterally encapsulates and is in direct contact with the second dielectric layer of the second die. The first conductive pads of the first die are in physical contact with a first portion of the second conductive pads of the second die.
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公开(公告)号：US11664315B2
公开(公告)日：2023-05-30
申请号：US17199412
申请日：2021-03-11
Inventor： Hao-Yi Tsai , Tzuan-Horng Liu , Ting Hao Kuo
IPC: H01L23/538 , H01L23/00 , H01L23/31 , H01L23/48 , H01L25/065
CPC classification number: H01L23/5381 , H01L23/3107 , H01L23/481 , H01L24/08 , H01L24/24 , H01L25/0655 , H01L2224/08145 , H01L2224/24225
Abstract: A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.
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