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公开(公告)号：US20230354613A1
公开(公告)日：2023-11-02
申请号：US18340933
申请日：2023-06-26
发明人： Bi-Shen Lee , Tzu-Yu Lin , Yi-Yang Wei , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： In some embodiments, the present disclosure relates to a memory device including a semiconductor substrate, a first electrode disposed over the semiconductor substrate, a ferroelectric layer disposed between the first electrode and the semiconductor substrate, and a first stressor layer separating the first electrode from the ferroelectric layer. The first stressor layer has a coefficient of thermal expansion greater than that of the ferroelectric layer.
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公开(公告)号：US20240071813A1
公开(公告)日：2024-02-29
申请号：US17895286
申请日：2022-08-25
发明人： Tzu-Yu Lin , Yao-Wen Chang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/06 , H01L27/105
CPC分类号： H01L21/76802 , H01L21/76826 , H01L21/76843 , H01L21/76879 , H01L23/5226 , H01L23/5283 , H01L23/53266 , H01L27/0688 , H01L27/1052
摘要： A dielectric structure is formed over a layer than contains a conductive component. An opening is formed in the dielectric structure. The opening exposes an upper surface of the conductive component. A first deposition process is performed that deposits a first conductive layer over the dielectric structure and partially in the opening. A treatment process is performed on a first portion of the first conductive layer formed over the dielectric structure. The treatment process introduces a non-metal material to the first portion of the first conductive layer. After the treatment process has been performed, a second deposition process is performed that at least partially fills the opening with a second conductive layer without trapping a gap therein.
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公开(公告)号：US20240038265A1
公开(公告)日：2024-02-01
申请号：US18150281
申请日：2023-01-05
发明人： Tzu-Yu Lin , Yao-Wen Chang
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
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公开(公告)号：US20240355358A1
公开(公告)日：2024-10-24
申请号：US18763154
申请日：2024-07-03
发明人： Tzu-Yu Lin , Yao-Wen Chang
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
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公开(公告)号：US12119035B2
公开(公告)日：2024-10-15
申请号：US18150281
申请日：2023-01-05
发明人： Tzu-Yu Lin , Yao-Wen Chang
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.
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公开(公告)号：US20240298555A1
公开(公告)日：2024-09-05
申请号：US18177397
申请日：2023-03-02
发明人： Sheng-Siang Ruan , Chia-Wen Zhong , Tzu-Yu Lin , Yao-Wen Chang , Ching Ju Yang , Chin I Wang
CPC分类号： H10N70/8416 , H10N70/023 , H10N70/026 , H10N70/063 , H10N70/245 , H10N70/883 , H01J37/32091 , H01J2237/3321
摘要： A semiconductor device that includes a semiconductor substrate, a bottom electrode over the semiconductor substrate, a switching layer over the bottom electrode, a metal ion source layer over the switching layer, and a top electrode over the metal ion source layer. The switching layer includes a compound having aluminum, oxygen, and nitrogen.
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7.发明公开公开(公告)号：US20240021561A1
公开(公告)日：2024-01-18
申请号：US18446571
申请日：2023-08-09
发明人： Tzu-Yu Lin , Yao-Wen Chang , Chia-Wen Zhong , Yen-Liang Lin
IPC分类号： H01L23/00 , H01L23/522 , H01L21/3213 , H01L27/15
CPC分类号： H01L24/20 , H01L23/5226 , H01L24/13 , H01L21/32139 , H01L27/15 , H01L24/19 , H01L2224/13019 , H01L2224/2101
摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes an interconnect structure overlying a semiconductor substrate and comprising a conductive wire. A passivation structure overlies the interconnect structure. An upper conductive structure overlies the passivation structure and comprises a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates through the first conductive layer and the passivation structure to the conductive wire.
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公开(公告)号：US20220278115A1
公开(公告)日：2022-09-01
申请号：US17385576
申请日：2021-07-26
发明人： Yi Yang Wei , Tzu-Yu Lin , Bi-Shen Lee , Hai-Dang Trinh , Hsing-Lien Lin , Hsun-Chung Kuang
IPC分类号： H01L27/11507 , H01L49/02
摘要： Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.
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公开(公告)号：US20230363178A1
公开(公告)日：2023-11-09
申请号：US18353988
申请日：2023-07-18
发明人： Tzu-Yu Lin , Chia-Wen Zhong , Yao-Wen Chang
CPC分类号： H10B53/30 , H01L28/75 , H01L28/57 , H10B12/033
摘要： 1. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.
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