SPACER FILM SCHEME FORM POLARIZATION IMPROVEMENT

    公开(公告)号:US20240038265A1

    公开(公告)日:2024-02-01

    申请号:US18150281

    申请日:2023-01-05

    IPC分类号: G11B9/02 H10B51/30

    CPC分类号: G11B9/02 H10B51/30

    摘要: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

    SPACER FILM SCHEME FORM POLARIZATION IMPROVEMENT

    公开(公告)号:US20240355358A1

    公开(公告)日:2024-10-24

    申请号:US18763154

    申请日:2024-07-03

    IPC分类号: G11B9/02 H10B51/30

    CPC分类号: G11B9/02 H10B51/30

    摘要: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

    Spacer film scheme for polarization improvement

    公开(公告)号:US12119035B2

    公开(公告)日:2024-10-15

    申请号:US18150281

    申请日:2023-01-05

    IPC分类号: G11B9/02 H10B51/30

    CPC分类号: G11B9/02 H10B51/30

    摘要: The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

    Ferroelectric Memory Device and Method of Manufacturing the Same

    公开(公告)号:US20220278115A1

    公开(公告)日:2022-09-01

    申请号:US17385576

    申请日:2021-07-26

    IPC分类号: H01L27/11507 H01L49/02

    摘要: Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

    BOTTOM-ELECTRODE INTERFACE STRUCTURE FOR MEMORY

    公开(公告)号:US20230363178A1

    公开(公告)日:2023-11-09

    申请号:US18353988

    申请日:2023-07-18

    IPC分类号: H10B53/30 H10B12/00

    摘要: 1. Various embodiments of the present disclosure are directed towards a ferroelectric random-access memory (FeRAM) cell or some other suitable type of memory cell comprising a bottom-electrode interface structure. The memory cell further comprises a bottom electrode, a switching layer over the bottom electrode, and a top electrode over the switching layer. The bottom-electrode interface structure separates the bottom electrode and the switching layer from each other. Further, the interface structure is dielectric and is configured to block or otherwise resist metal atoms and/or impurities in the bottom electrode from diffusing to the switching layer. By blocking or otherwise resisting such diffusion, leakage current may be decreased. Further, endurance of the memory cell may be increased.