公开(公告)号：US5773340A

公开(公告)日：1998-06-30

申请号：US563335

申请日：1995-11-28

申请人： Takahiro Kumauchi ,  Takashi Hashimoto ,  Osamu Kasahara ,  Satoshi Yamamoto ,  Yoichi Tamaki ,  Takeo Shiba ,  Takashi Uchino

发明人： Takahiro Kumauchi ,  Takashi Hashimoto ,  Osamu Kasahara ,  Satoshi Yamamoto ,  Yoichi Tamaki ,  Takeo Shiba ,  Takashi Uchino

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L21/8249 ,  Y10S148/152

摘要： A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

摘要翻译： 公开了一种制造具有磷掺杂多晶硅发射极电极的改进的双极晶体管或BiCMOS的方法。 该方法包括形成发射电极，其中磷掺杂的非晶硅膜在不高于540℃的温度下沉积，然后在600℃至750℃的温度下进行低温退火处理， 将非晶硅转化为多晶硅，将存在于非晶硅膜中的磷扩散到基极区域，形成发射极区域，然后在900℃〜950℃的温度下进行高温/短时退火处理 从而提高了掺杂多晶硅的多晶硅基极或MOSFET的源极 - 漏极区域中的杂质的活化速率。

公开(公告)号：US5793097A

公开(公告)日：1998-08-11

申请号：US519096

申请日：1995-08-24

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L29/00 ,  H01L23/48 ,  H01L29/76

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US20050101097A1

公开(公告)日：2005-05-12

申请号：US11000092

申请日：2004-12-01

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/20 ,  H01L21/8222

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US6133094A

公开(公告)日：2000-10-17

申请号：US123405

申请日：1998-07-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01C7/06 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US06610569B1

公开(公告)日：2003-08-26

申请号：US09649504

申请日：2000-08-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L21336

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且多晶第一硅层的抗蚀剂的温度依赖性为正，而 第二多晶层具有电阻的负温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US06835632B2

公开(公告)日：2004-12-28

申请号：US10460215

申请日：2003-06-13

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L2120

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US06524924B1

公开(公告)日：2003-02-25

申请号：US09123406

申请日：1998-07-28

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L2120

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的至少两层结构，并且第一多晶硅层具有正电温度依赖性而第二 多晶层具有电阻的负温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US07238582B2

公开(公告)日：2007-07-03

申请号：US11000092

申请日：2004-12-01

申请人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

发明人： Hiromi Shimamoto ,  Takashi Uchino ,  Takeo Shiba ,  Kazuhiro Ohnishi ,  Yoichi Tamaki ,  Takashi Kobayashi ,  Toshiyuki Kikuchi ,  Takahide Ikeda

IPC分类号： H01L21/8222

CPC分类号： H01L27/0652 ,  H01L27/0688 ,  H01L28/20

摘要： The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.

摘要翻译： 本发明提供了一种其电阻值被控制的多晶硅导电结构（例如电阻器），并且可以相对于任何电阻值而言可以变化较小并且对温度的依赖性较小，及其制造方法。 使用至少包括具有大晶粒尺寸的第一多晶硅层和小晶粒尺寸的第二多晶硅层的两层结构，并且第一多晶硅层具有正的温度对电阻的依赖性，而第二多晶硅层的第二 多晶硅层具有负电阻的温度依赖性，反之亦然。 此外，可以通过高剂量离子注入和退火，或者通过在不同温度下的化学气相沉积来沉积这些层，形成大晶粒和小晶粒层，可以形成大晶粒尺寸的多晶硅层。

公开(公告)号：US20100229378A1

公开(公告)日：2010-09-16

申请号：US12293646

申请日：2007-03-12

申请人： Takashi Uchino ,  Tadashi Shinozaki ,  Norifumi Eguchi ,  Naoki Yamauchi ,  Masao Hidaka ,  Toru Nakazono

发明人： Takashi Uchino ,  Tadashi Shinozaki ,  Norifumi Eguchi ,  Naoki Yamauchi ,  Masao Hidaka ,  Toru Nakazono

IPC分类号： B23P19/00

CPC分类号： H05K13/0478 ,  H01L21/67144 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/07802 ,  H05K13/085 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  H01L2224/83

摘要： A challenge to be met by the present invention is to provide an electronic component mounting apparatus and an electronic component mounting method that enable a reduction in the frequency of operation required with switching of a component type, to thus enhance productivity.In component mount operation for taking chips of component types A, B, and C out of a component supply portion by means of a single mount head and mounting the chips on two substrates held by a first lane and a second lane, when a subsequently-carried-in subsequent substrate has come to be able to undergo component mount operation before completion of processing pertaining to a preceding substrate mount process in which component mount operation is carried out on a previously-carried-in preceding substrate among a plurality of substrates, processing pertaining to a subsequent substrate mount process is started by taking, as mount start components, chips already serving as targets of component mount operation for the preceding substrate at this timing, and processing pertaining to the preceding substrate mount process during which mounting is not yet completed is continually carried out. Thereby, the frequency of operation required with switching of a component type, such as replacement of a nozzle, can be reduced.

摘要翻译： 本发明要解决的课题是提供一种电子部件安装装置和电子部件安装方法，其能够降低部件类型的切换所需的操作频率，从而提高生产率。 在用于通过单个安装头从组件供应部分中取出组件类型A，B和C的芯片的组件安装操作中，并且将芯片安装在由第一通道和第二通道保持的两个基板上， 随后的衬底已经能够在完成与之前的衬底安装工艺相关的处理之前进行组件安装操作，其中在多个衬底之间对先前存在的在前衬底进行组件安装操作，处理 关于随后的基板安装工艺，通过作为安装启动部件开始已经作为前面基板的部件安装操作的目标的芯片，以及与之前的基板安装处理有关的处理，其中安装尚未完成 不断进行 由此，可以减少切换喷嘴等部件的切换所需的操作频率。

公开(公告)号：US07795767B2

公开(公告)日：2010-09-14

申请号：US12401834

申请日：2009-03-11

申请人： Tetsuji Ueta ,  Hiroaki Sagara ,  Yukifumi Yamaguchi ,  Takashi Uchino ,  Kenji Taguchi

发明人： Tetsuji Ueta ,  Hiroaki Sagara ,  Yukifumi Yamaguchi ,  Takashi Uchino ,  Kenji Taguchi

IPC分类号： H02K11/00

CPC分类号： H02K3/522 ,  H02K1/148 ,  H02K5/225 ,  H02K2203/09 ,  H02K2203/12

摘要： An aspect of the invention provides a motor that comprises: a stator including multiple motor coils; multiple bus rings configured to distribute currents of different phases to the motor coils; and a ring-shaped bus ring holder in which multiple holding grooves configured to hold the respective bus rings are formed, wherein: each of the motor coils includes an insulator around which a wound wire is wound; the insulator includes an outer flange formed at an outer side of the wound wire in a radial direction of the motor and extending in an axial direction of the motor; and the bus ring holder is arranged at an outer side of the outer flange in the radial direction of the motor, and contiguous to the outer flange.

摘要翻译： 本发明的一个方面提供了一种电动机，其包括：定子，包括多个电动机线圈; 多个总线环配置成将不同相的电流分配到电动机线圈; 以及环形总线环保持器，其中形成有用于保持各个总线环的多个保持槽，其中：每个电动机线圈包括缠绕有绕线的绝缘体; 所述绝缘体包括沿所述绕线的外侧形成在所述电动机的径向方向上且沿所述电动机的轴向延伸的外凸缘; 并且所述总线环保持器沿所述电动机的径向布置在所述外凸缘的外侧，并且与所述外凸缘邻接。