公开(公告)号：US5773340A

公开(公告)日：1998-06-30

申请号：US563335

申请日：1995-11-28

申请人： Takahiro Kumauchi ,  Takashi Hashimoto ,  Osamu Kasahara ,  Satoshi Yamamoto ,  Yoichi Tamaki ,  Takeo Shiba ,  Takashi Uchino

发明人： Takahiro Kumauchi ,  Takashi Hashimoto ,  Osamu Kasahara ,  Satoshi Yamamoto ,  Yoichi Tamaki ,  Takeo Shiba ,  Takashi Uchino

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L21/8249 ,  Y10S148/152

摘要： A method of manufacturing an improved bipolar transistor or BiCMOS having a phosphorus-doped polysilicon emitter electrode is disclosed. The method comprises forming an emitter electrode wherein a phosphorus-doped amorphous silicon film is deposited at temperature not higher than 540.degree. C. and then subjected to low temperature annealing treatment at a temperature of 600.degree. C. to 750.degree. C., under which the amorphous silicon is converted to a polysilicon and the phosphorus present in the amorphous silicon film is diffused into a base region to form an emitter region, followed by high temperature/short time annealing treatment at a temperature of 900.degree. C. to 950.degree. C. so that an activation rate of an impurity in a boron-doped polysilicon base electrode or source-drain regions of MOS.cndot.FET is improved.

摘要翻译： 公开了一种制造具有磷掺杂多晶硅发射极电极的改进的双极晶体管或BiCMOS的方法。 该方法包括形成发射电极，其中磷掺杂的非晶硅膜在不高于540℃的温度下沉积，然后在600℃至750℃的温度下进行低温退火处理， 将非晶硅转化为多晶硅，将存在于非晶硅膜中的磷扩散到基极区域，形成发射极区域，然后在900℃〜950℃的温度下进行高温/短时退火处理 从而提高了掺杂多晶硅的多晶硅基极或MOSFET的源极 - 漏极区域中的杂质的活化速率。

公开(公告)号：US5846869A

公开(公告)日：1998-12-08

申请号：US685844

申请日：1996-07-24

申请人： Takashi Hashimoto ,  Hideo Miura ,  Toshiyuki Kikuchi ,  Toshiyuki Mine ,  Yoichi Tamaki ,  Takahiro Kumauchi

发明人： Takashi Hashimoto ,  Hideo Miura ,  Toshiyuki Kikuchi ,  Toshiyuki Mine ,  Yoichi Tamaki ,  Takahiro Kumauchi

IPC分类号： H01L29/73 ,  H01L21/205 ,  H01L21/306 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/732 ,  H01L29/737 ,  H01L21/301

CPC分类号： H01L21/02052 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/8222 ,  H01L29/66272 ,  H01L29/7375 ,  Y10S438/906

摘要： A method of manufacturing a bipolar transistor having an improved polysilicon emitter is disclosed. More specifically, hydrogen terminations or OH group terminations adhered (bonded) to an emitter-forming region are eliminated by a heat treatment in an inert gas atmosphere before forming emitter polysilicon. Subsequently, an amorphous silicon film for forming an emitter polysilicon is formed at a low temperature.

摘要翻译： 公开了一种制造具有改进的多晶硅发射极的双极晶体管的方法。 更具体地，在形成发射极多晶硅之前，通过在惰性气体气氛中的热处理来消除粘附（结合）到发射体形成区域的氢端基或OH基端基。 随后，在低温下形成用于形成发射极多晶硅的非晶硅膜。

公开(公告)号：US07224034B2

公开(公告)日：2007-05-29

申请号：US10978469

申请日：2004-11-02

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术：在p上的栅极绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜 （半导体衬底），帽绝缘膜，W膜和WN膜被蚀刻，并且进行其下面的多晶硅膜的过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US06649956B2

公开(公告)日：2003-11-18

申请号：US10227799

申请日：2002-08-27

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

公开(公告)号：US06483136B1

公开(公告)日：2002-11-19

申请号：US09446302

申请日：2000-04-14

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Isamu Asano ,  Norio Hasegawa ,  Keizo Kawakita

IPC分类号： H01L2972

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate (1) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

摘要翻译： 在其中形成有用于选择构成DRAM的存储单元的DRAM存储单元的金属绝缘体半导体场效应晶体管（MISFET）（Qs）的有源区域（L）被布置成具有岛状图案， 在半导体衬底（1）的一个主表面上沿X方向线性地延伸。 存储单元选择MISFET（Qs）具有在半导体衬底（1）的主表面上沿着Y方向延伸的绝缘栅电极（字线WL），沿着其长度保持相同的宽度， 栅电极被布置成以比所述宽度窄的预定距离或间距与与其相邻的另一个栅电极（7）（字线WL）相对。 此外，位线（BL）以这样的方式设置在存储单元选择MISFET（Qs）上，使得位线在半导体衬底（1）的主表面上沿X方向以相同的宽度延伸，并且 以比所述宽度更宽的距离或间距来对置其相邻位线（BL）。

公开(公告)号：US5981369A

公开(公告)日：1999-11-09

申请号：US865864

申请日：1997-05-30

申请人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

发明人： Makoto Yoshida ,  Takahiro Kumauchi ,  Yoshitaka Tadaki ,  Kazuhiko Kajigaya ,  Hideo Aoki ,  Isamu Asano

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L21/44

CPC分类号： H01L21/823871 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/76849 ,  H01L21/76853 ,  H01L27/10855 ,  H01L27/10894

摘要： In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500.degree. C. or lower at a step after the MISFET has been formed.

摘要翻译： 在制造具有MISFET的半导体集成电路器件的工艺中，为了通过减少热处理步骤的数量来实现MISFET的源极/漏极与半导体衬底之间的浅结，可以将所有导电膜沉积 在形成MISFET之后的步骤中，在半导体基板上淀积5​​00℃以下的温度。 此外，要沉积在半导体衬底上的所有绝缘膜在形成MISFET之后的步骤中在500℃或更低的温度下沉积。

公开(公告)号：US08138536B2

公开(公告)日：2012-03-20

申请号：US12647187

申请日：2009-12-24

申请人： Satoru Isogai ,  Takahiro Kumauchi

发明人： Satoru Isogai ,  Takahiro Kumauchi

IPC分类号： H01L21/108

CPC分类号： H01L28/60 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.

摘要翻译： 提供一种半导体器件，包括：多个电容器，每个电容器包括具有内壁和外壁的圆筒形下电极和经由电容电介质膜覆盖下电极的外壁的上电极; 以及支撑膜，其具有掩埋在由所述下部电极的内壁包围的内部区域中的掩埋部，以及支撑部，其一部分位于所述内部区域内，其余部分位于所述内部区域的外侧 。 支撑部分通过覆盖下电极的上壁和外壁的内壁和下壁的外壁来夹住下端电极在上端两端的上端。

公开(公告)号：US07687849B2

公开(公告)日：2010-03-30

申请号：US12128796

申请日：2008-05-29

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L29/788

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了一种通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US06828242B2

公开(公告)日：2004-12-07

申请号：US10223317

申请日：2002-08-20

申请人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

发明人： Hiroshi Kujirai ,  Kousuke Okuyama ,  Kazuhiro Hata ,  Kiyonori Oyu ,  Ryo Nagai ,  Hiroyuki Uchiyama ,  Takahiro Kumauchi ,  Teruhisa Ichise

IPC分类号： H01L21302

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10814 ,  H01L27/10873 ,  H01L29/4941

摘要： Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.

摘要翻译： 公开了通过减少组成MISFET的多金属栅极的金属的污染来减少泄漏电流的技术。 在p型阱（半导体衬底），帽绝缘膜，W膜和WN膜上的栅绝缘膜上形成的多晶硅膜，WN膜，W膜和帽绝缘膜是 进行蚀刻，并对其下面的多晶硅膜进行过蚀刻。 然后，在这些膜的侧壁上形成侧壁膜。 此后，在以侧壁膜为掩模蚀刻多晶硅膜之后，在氧化气氛中进行热处理，在多晶硅膜的侧壁上形成有氧化膜。 结果，可以减少由W和W氧化物引起的栅绝缘膜上的污染，并且这些材料向半导体衬底（p型阱）的扩散以及由此导致的漏电流的增加 被阻止

公开(公告)号：US08581315B2

公开(公告)日：2013-11-12

申请号：US13366391

申请日：2012-02-06

申请人： Satoru Isogai ,  Takahiro Kumauchi

发明人： Satoru Isogai ,  Takahiro Kumauchi

IPC分类号： H01L21/108

CPC分类号： H01L28/60 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： To provide a semiconductor device including: plural capacitors each including a cylindrical lower electrode having an internal wall and an external wall, and an upper electrode that covers the external wall of the lower electrode via a capacitance dielectric film; and a supporting film having a buried portion buried in an internal region surrounded by the internal wall of the lower electrode, and a supporting portion a part of which is positioned within the internal region and remaining parts of which are positioned at outside of the internal region. The supporting portion sandwiches an upper end of the lower electrode at both ends of the upper end by covering the internal wall and the external wall of the upper end of the lower electrode.

摘要翻译： 提供一种半导体器件，包括：多个电容器，每个电容器包括具有内壁和外壁的圆筒形下电极和经由电容电介质膜覆盖下电极的外壁的上电极; 以及支撑膜，其具有掩埋在由所述下部电极的内壁包围的内部区域中的掩埋部，以及支撑部，其一部分位于所述内部区域内，其余部分位于所述内部区域的外侧 。 支撑部分通过覆盖下电极的上壁和外壁的内壁和下壁的外壁来夹住下端电极在上端两端的上端。