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公开(公告)号：US5818797A
公开(公告)日：1998-10-06
申请号：US908975
申请日：1997-08-08
CPC分类号： G04F10/00
摘要： To provide a time measuring apparatus which is compact and capable of highly accurate measurements, on a semiconductor chip, flip-flops constituting a delayed-signal holding circuit of a first channel and flip-flops constituting a delayed-signal holding circuit of a second channel are disposed alternatingly and in a single row in a circuit region of the delayed-signal holding circuits to latch delayed signals from a pulse-circulating circuit, and flip-flops for latching the same delay signals are mutually adjacent. Due to this, distances between the pulse-circulating circuit and the respective delayed-signal holding circuits become equal, and delay signals having no deviation in delay due to difference in wiring length are supplied to the respective channels, and so uniform measurement can be performed between the respective channels.
摘要翻译： 为了提供紧凑且能够高精度测量的时间测量装置，在半导体芯片上，构成第一通道的延迟信号保持电路的触发器和构成第二通道的延迟信号保持电路的触发器 在延迟信号保持电路的电路区域中交替且单行地设置，以锁存来自脉冲循环电路的延迟信号，并且用于锁存相同延迟信号的触发器相互相邻。 由此，脉冲循环电路和各延迟信号保持电路之间的距离变得相等，并且由于布线长度的差异而没有延迟偏差的延迟信号被提供给各个通道，因此可以进行均匀的测量 在各个通道之间。
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2.发明申请Method of placing delay units of pulse delay circuit on programmable logic device 有权在可编程逻辑器件上放置脉冲延迟电路的延迟单元的方法公开(公告)号：US20100237923A1
公开(公告)日：2010-09-23
申请号：US12661156
申请日：2010-03-11
IPC分类号： H03H11/26 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string.
摘要翻译： 将脉冲延迟电路的延迟单元放置在具有每个单元串中的逻辑单元的可编程逻辑器件上的方法具有将每个延迟单元布置在器件的一个逻辑单元中的步骤，使得延迟单元放置在相应的特定单元中 在行方向排列的串和将延迟单元串联连接的直线延迟线的步骤，使得以连接顺序放置在特定单元串中的延迟单元在行方向上对齐。 在该装置中，不同单元串的两个逻辑单元之间的行上的串间传输延迟时间与一个单元串的两个逻辑单元之间的一行上的串内传输延迟时间不同。
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公开(公告)号：US07755530B2
公开(公告)日：2010-07-13
申请号：US12218531
申请日：2008-07-16
IPC分类号： H03M1/60
CPC分类号： H03M1/502
摘要： An A/D converter has a series of M delay units through which a pulse signal is transmitted while being delayed in each delay unit by a delay time depending on a level of an analog signal. A unit of the converter latches the pulse signal outputted from each delay unit at N sampling times to hold M×N latched data. Another unit of the converter receives the M×N pieces of latched data as a piece of combined data composed of the latched data arranged in an order corresponding to an arranging order of M×N sampling points in the pulse signal, converts the combined data into numeral data, corresponding to a position of the pulse signal in the delay units, at one time, and produces converted digital data corresponding to the level of the analog signal from the numeral data.
摘要翻译： A / D转换器具有一系列M个延迟单元，根据模拟信号的电平，在每个延迟单元中延迟延迟时间，脉冲信号通过该延迟单元被发送。 转换器的单位在N个采样时间中锁存从每个延迟单元输出的脉冲信号，以保持M×N个锁存数据。 转换器的另一单元接收M×N个锁存数据作为由按脉冲信号中的M×N个采样点的排列次序排列的锁存数据组成的一组合数据，将组合数据转换成 数字数据对应于延迟单元中的脉冲信号的位置，并且产生与来自数字数据的模拟信号的电平对应的转换的数字数据。
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4.发明授权Control signal generating circuit enabling value of period of a generated clock signal to be set as the period of a reference signal multiplied or divided by an arbitrary real number 有权控制信号发生电路使所生成的时钟信号的周期值能够被设置为与任意实数相乘或除以的参考信号的周期公开(公告)号：US07733152B2
公开(公告)日：2010-06-08
申请号：US12324287
申请日：2008-11-26
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： G06F1/04
CPC分类号： H03K3/0315 , H03K23/425
摘要： A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtain control data specifying a required period of a clock signal as a value having an integer part and a fractional part. The control data are used to select the timings of specific traversal signal, and the clock signal is generated based these selected timings, with the timing selection being repetitively adjusted in accordance with the fractional part of the control data.
摘要翻译： 脉冲信号在延迟元件环周围循环，各个遍历信号由延迟元件依次输出。 将参考信号的周期相乘或除以实数，以获得指定时钟信号的所需周期的控制数据，作为具有整数部分和小数部分的值。 控制数据用于选择特定遍历信号的定时，并且基于这些选择的定时生成时钟信号，根据控制数据的小数部分重复地调整定时选择。
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公开(公告)号：US07671313B2
公开(公告)日：2010-03-02
申请号：US11393818
申请日：2006-03-31
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
CPC分类号： H04N5/37455
摘要： An image sensor has plural array blocks B1 to B20 arranged in a two dimensional (2D) arrangement. Each array block has a sub array and a corresponding analogue to digital (A/D) converter for performing an A/D conversion of light signals (or detection signals) output from the sub array. The sub array has plural picture element cells arranged in a 2D arrangement. Each A/D converter has a pulse delay circuit having delay units of plural stages connected in series. Each delay unit delays an input pulse by a delay time corresponding to a level of the light signals received from the sub array. A pulse delay type A/D converter is used as the A/D converter, which outputs the number of the delay units as an A/D conversion data item through which the input pulse passes for a measurement time period.
摘要翻译： 图像传感器具有以二维（2D）布置排列的多个阵列块B1至B20。 每个阵列块具有子阵列和相应的模数（A / D）转换器，用于执行从子阵列输出的光信号（或检测信号）的A / D转换。 子阵列具有以2D排列布置的多个像素单元。 每个A / D转换器具有串联连接的多级延迟单元的脉冲延迟电路。 每个延迟单元将输入脉冲延迟与从子阵列接收的光信号的电平相对应的延迟时间。 使用脉冲延迟型A / D转换器作为A / D转换器，其输出延迟单元的数量作为输入脉冲经过测量时间段的A / D转换数据项。
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6.发明申请Method for controlling delay time of pulse delay circuit and pulse delay circuit thereof 有权用于控制脉冲延迟电路的延迟时间及其脉冲延迟电路的方法公开(公告)号：US20090135040A1
公开(公告)日：2009-05-28
申请号：US12292761
申请日：2008-11-25
CPC分类号： H03K5/133
摘要： An inverter circuit configuring a delay unit is a so-called CMOS transistor including a PMOS transistor and an NMOS transistor, of which respective gates are interconnected and respective drains are interconnected. The source and a back gate of the NMOS transistor are connected to the ground. The source of the PMOS transistor is connected to a positive drive terminal and controlled by an analog input signal. The back gate of the PMOS transistor is connected to a control terminal and controlled by a control signal.
摘要翻译： 配置延迟单元的逆变器电路是所谓的CMOS晶体管，其包括PMOS晶体管和NMOS晶体管，其中相应的栅极互连并且相应的漏极互连。 NMOS晶体管的源极和背栅极连接到地。 PMOS晶体管的源极连接到正极驱动端子并由模拟输入信号控制。 PMOS晶体管的背栅极连接到控制端子并由控制信号控制。
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7.发明授权公开(公告)号：US07292175B2
公开(公告)日：2007-11-06
申请号：US11407211
申请日：2006-04-20
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H03M1/60
摘要： For testing an A/D converter circuit including a pulse delay circuit constituted by a plurality of cascade-connected delay units, and an encoding circuit configured to count the number of the delay units through which the input pulse signal passes within a predetermined measuring time and to output a digital signal representing the counted number, the method includes the steps of setting the A/D converter circuit in a test mode where the measuring time is set at a short test-use sampling period, applying the input pulse signal to each of serial delay blocks each of which is constituted by a predetermined number of the delay units, and determining good and bad of the A/D converter circuit on the basis of digital signals outputted from the encoding circuit representing the numbers of the delay units through which the input pulse signal has passed within each of the serial delay blocks.
摘要翻译： 为了测试包括由多个级联连接的延迟单元构成的脉冲延迟电路的A / D转换电路，以及编码电路，被配置为对在预定测量时间内输入脉冲信号通过的延迟单元的数量进行计数;以及 为了输出表示所述计数的数字信号，所述方法包括以下步骤：将所述A / D转换电路设定为测试时间设定在短的测试使用采样周期的测试模式，将所述输入脉冲信号施加到 串行延迟块，每个延迟块由预定数量的延迟单元构成，并且基于从编码电路输出的数字信号确定A / D转换器电路的好坏，所述数字信号表示延迟单元的数量， 输入脉冲信号已通过每个串行延迟块。
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8.发明申请TAD A/D converter in which pulse delay circuit is initialized prior to each conversion operation for deriving an output digital value 有权TAD A / D转换器，其中脉冲延迟电路在每个转换操作之前被初始化以导出输出数字值公开(公告)号：US20070120723A1
公开(公告)日：2007-05-31
申请号：US11606134
申请日：2006-11-30
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H03M1/12
摘要： In a TAD (Time Analog-to-Digital) type of A/D converter in which delay units of a pulse delay circuit successively transfer a pulse signal during each of successive measurement intervals, with each delay unit applying an amount of delay determined by an analog input signal voltage, it is ensured that each new measurement interval begins as soon as the pulse delay circuit has become restored to an initialized condition after the preceding measurement interval. Output values expressing the number of delay units traversed by the pulse signal during a measurement interval are used directly as digital values representing the analog input signal voltage level.
摘要翻译： 在TAD（时间模数数字）类型的A / D转换器中，其中脉冲延迟电路的延迟单元在每个连续测量间隔期间连续传送脉冲信号，每个延迟单元施加由 模拟输入信号电压，一旦脉冲延迟电路恢复到先前测量间隔之后的初始化状态，则确保每个新的测量间隔开始。 表示在测量间隔期间由脉冲信号经过的延迟单元的数量的输出值直接用作表示模拟输入信号电压电平的数字值。
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公开(公告)号：US06891491B2
公开(公告)日：2005-05-10
申请号：US10791649
申请日：2004-03-02
申请人： Mitsuo Nakamura , Takamoto Watanabe , Sumio Masuda
发明人： Mitsuo Nakamura , Takamoto Watanabe , Sumio Masuda
CPC分类号： H03M1/1042 , H03M1/50 , H03M1/502
摘要： A method for correcting A/D converted output data which corrects digital data obtained by A/D conversion of an analog signal, comprising forming an at least first order polynomial curve approximating an input/output characteristic curve of A/D conversion in a range of input of the analog signal, setting an ideal input/output characteristic line of A/D conversion, deriving a conversion equation for converting coordinates of a point on the approximation polynomial curve to a point of the ideal input/output characteristic line for the same analog signal value, and using this conversion equation to convert A/D converted digital data so as to correct non-linearity of the output data.
摘要翻译： 一种用于校正A / D转换的输出数据的方法，该数据校正通过模拟信号的A / D转换而获得的数字数据，包括形成在A / D转换范围内近似A / D转换的输入/输出特性曲线的至少一阶多项式曲线 输入模拟信号，设置A / D转换的理想输入/输出特性线，得出用于将近似多项式曲线上的点的坐标转换为相同模拟的理想输入/输出特性线的点的转换方程 信号值，并使用该转换方程转换A / D转换的数字数据，以校正输出数据的非线性。
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公开(公告)号：US06879278B2
公开(公告)日：2005-04-12
申请号：US10854297
申请日：2004-05-26
CPC分类号： H03M1/206 , G04F10/005 , H03M1/502
摘要： An A/D converter for driving a plurality of delay units forming a pulse delay circuit by an analog input signal Vin and digitalizing the number of delay units through which a pulse signal passes in the pulse delay circuit at predetermined timings, provided with a plurality of pulse position digitalizing units used for A/D conversion and inputting delay pulses from the delay units of the pulse delay circuit to the pulse position digitalizing units through an inverter group comprised of inverters with different inversion levels (switching threshold level) by different input timings. The digital data obtained by the pulse position digitalizing units are added by an adder.
摘要翻译： 一种A / D转换器，用于通过模拟输入信号Vin驱动形成脉冲延迟电路的多个延迟单元，并且将预定时间脉冲信号通过脉冲信号的延迟单元的数量化，并设置多个延迟单元 用于A / D转换的脉冲位置数字化单元，并且通过由不同输入定时具有不同反相电平（开关阈值电平）的反相器组成的反相器组将延迟脉冲从脉冲延迟电路的延迟单元输入到脉冲位置数字化单元。 由脉冲位置数字化单元获得的数字数据由加法器相加。
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