Computer containing clock source using a PLL synthesizer
    10.
    发明授权
    Computer containing clock source using a PLL synthesizer 失效
    使用PLL合成器的计算机包含时钟源

    公开(公告)号:US06845462B2

    公开(公告)日:2005-01-18

    申请号:US10245096

    申请日:2002-09-17

    摘要: A computer of the present invention contains: a CPU; plural peripheral devices controlled by the CPU; a data transmission bus between the CPU and the peripheral devices and between the peripheral devices; and a clock signal source for supplying clock signals for CPU operation and data transmission. The clock signal source contains a PLL synthesizer, and two clock signals (one for the CPU and the other for the bus) are outputted from the PLL synthesizer to stop unnecessary signals (other than the clock signals) from being produced.

    摘要翻译: 本发明的计算机包括:CPU; 由CPU控制的多个外围设备; 在CPU和外围设备之间以及外围设备之间的数据传输总线; 以及用于提供用于CPU操作和数据传输的时钟信号的时钟信号源。 时钟信号源包含PLL合成器,从PLL合成器输出两个时钟信号(一个用于CPU,另一个用于总线),以阻止不必要的信号(时钟信号除外)产生。