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公开(公告)号：US5616079A
公开(公告)日：1997-04-01
申请号：US381992
申请日：1995-02-15
CPC分类号： A63F13/53 , A63F13/005 , A63F13/245 , A63F13/803 , G06T15/005 , A63F2300/1062 , A63F2300/66 , A63F2300/8017
摘要： An objective of the present invention is to provide a 3D games machine that can form a high-quality pseudo-3D image in real time. Segmented map information relating to a map that configures a game space is stored in a map information storage unit (110). This segmented map information contains map position information and an object number. A game space setting unit (104) reads out image information on the map from an object image information storage unit (120) on the basis of this object number, to set the games space. In this case, a plurality of types of segmented map information, of different numbers of segments, is stored in the map information storage unit (110). The game space setting unit (104) sets the game space by reading out segmented map information with a smaller number of segments as the distance between the vehicle operated by the player and the segmented map increases.
摘要翻译： PCT No.PCT / JP94 / 00972 Sec。 371日期1995年2月15日 102（e）日期1995年2月15日PCT提交1994年6月16日PCT公布。 WO94 / 28989 PCT公开 日期1994年12月22日本发明的目的是提供一种能够实时形成高质量伪3D图像的3D游戏机。 与配置游戏空间的地图相关的分割地图信息存储在地图信息存储单元（110）中。 该分割地图信息包含地图位置信息和对象编号。 游戏空间设定单元（104）基于该对象编号从对象图像信息存储单元（120）读出地图上的图像信息，以设定游戏空间。 在这种情况下，在地图信息存储单元（110）中存储多个不同数量的片段的分割地图信息。 游戏空间设定单元（104）通过在玩家操作的车辆与分割地图之间的距离增加的情况下通过读取具有较少数量的段的分割地图信息来设置游戏空间。
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2.发明申请FAILURE DETECTING METHOD, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLICATION SYSTEM 审中-公开故障检测方法，半导体器件和微型计算机应用系统公开(公告)号：US20110288807A1
公开(公告)日：2011-11-24
申请号：US13111942
申请日：2011-05-19
申请人： Takashi Iwase , Masamichi Fujito
发明人： Takashi Iwase , Masamichi Fujito
CPC分类号： G06F11/0751
摘要： The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected. Moreover, an actual state change in the circuit to be subjected to failure detection based on a change in the analog amount in the circuit to be subjected to failure detection is determined by the failure detection circuit, so that precision of failure detection is improved.
摘要翻译： 本发明旨在通过改变要进行故障检测的电路的模拟量来执行故障检测来提高故障检测的精度。 通过调谐电路在预定条件下改变要进行故障检测的电路的模拟量，并且基于要承受的电路中的模拟量的变化，进行故障检测的电路的状态变化 由故障检测电路确定故障检测，从而检测要进行故障检测的电路中的故障。 以这种方式，在不监视半导体装置的外部的故障检测电路的输出的情况下，可以检测到要进行故障检测的电路的故障。 此外，由故障检测电路确定基于故障检测的电路中的模拟量的变化而要进行故障检测的电路的实际状态变化，从而提高故障检测的精度。
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3.发明申请NONVOLATILE MEMORY, DATA PROCESSING APPARATUS, AND MICROCOMPUTER APPLICATION SYSTEM 有权非易失性存储器，数据处理设备和微处理器应用系统公开(公告)号：US20120002498A1
公开(公告)日：2012-01-05
申请号：US13171849
申请日：2011-06-29
申请人： Toru Matsushita , Ken Matsubara , Takashi Iwase , Hidenori Mitani , Jun Setogawa , Fumiko Yamada
发明人： Toru Matsushita , Ken Matsubara , Takashi Iwase , Hidenori Mitani , Jun Setogawa , Fumiko Yamada
IPC分类号： G11C5/14
摘要： Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. Accordingly, operational stability of the nonvolatile memory is realized.
摘要翻译： 实现了与电源电压电平相对应地设置的多个电源电压模式中的非易失性存储器的操作稳定性。 非易失性存储器配置有存储器阵列，电荷泵，用于选择电荷泵的输出电压的分配器，以及用于控制电荷泵和分配器的操作的定序器。 非易失性存储器还设置有分析器，其向定序器通知在与电源电压电平相对应地设置的多个电源电压模式中选择性地指定的电源电压模式，并且检测通知给 定序器和实际提供的电源电压，并且基于检测结果限制使用定序器的电荷泵和分配器的操作。 因此，实现了非易失性存储器的操作稳定性。
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公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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公开(公告)号：US07943124B2
公开(公告)日：2011-05-17
申请号：US11815136
申请日：2006-02-01
申请人： Itaru Moro , Takashi Iwase , Kuniyasu Ochiai , Masako Yajima , Masaki Terahara , Yoshitaka Nakamura , Mamoru Totsuka , Kiyoshi Yamada
发明人： Itaru Moro , Takashi Iwase , Kuniyasu Ochiai , Masako Yajima , Masaki Terahara , Yoshitaka Nakamura , Mamoru Totsuka , Kiyoshi Yamada
CPC分类号： C12N1/20 , A23L33/135 , A23V2002/00 , A23Y2300/25 , A61K35/745 , C12R1/225 , A23V2200/324 , A23V2200/3204
摘要： The present invention relates to a composition for immunostimulation useful for promoting IgA and secretory component productions in mucosal tissues, comprising, alone or in combination, a cell of bifidobacterium belonging to Bifidobacterium bifidum or a processed product thereof, wherein the bifidobacterium has an activity to stimulate secretory component production and a high activity to stimulate IgA production, for example, it is a Bifidobacterium bifidum OLB 6377 strain or Bifidobacterium bifidum OLB 6378 strain.
摘要翻译： 本发明涉及可用于促进粘膜组织中的IgA和分泌成分产生的免疫刺激用组合物，其包含单独或组合地属于双歧双歧杆菌的双歧杆菌细胞或其加工产物，其中双歧杆菌具有刺激活性 分泌成分的生成和刺激IgA生产的高活性，例如双歧双歧杆菌OLB 6377株或双歧双歧杆菌OLB 6378株。
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公开(公告)号：US20100080058A1
公开(公告)日：2010-04-01
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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公开(公告)号：US20080089146A1
公开(公告)日：2008-04-17
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi FUJITO , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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公开(公告)号：US08335112B2
公开(公告)日：2012-12-18
申请号：US12766603
申请日：2010-04-23
申请人： Takashi Kono , Ken Matsubara , Takashi Iwase
发明人： Takashi Kono , Ken Matsubara , Takashi Iwase
IPC分类号： G11C11/34
摘要： A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.
摘要翻译： 提供一种非易失性半导体存储器件，其可以以低消耗电流精确地读取数据。 闪速存储器响应于时钟信号的前沿根据外部地址信号选择存储器单元，并且响应于正常读取模式下的时钟信号的前沿从存储器单元读取数据，而在 用于执行具有比正常读取模式更低的功耗的读取操作的低速读取模式，响应于时钟信号的后沿从存储器单元读取数据。 因此，由于噪声电平在时钟信号的后沿已经下降，所以即使在低速读取模式中响应于时钟信号的前沿产生噪声，也可以准确地读取数据。
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公开(公告)号：US08144518B2
公开(公告)日：2012-03-27
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译： 半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的 保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。 布置构成双胞胎的两个存储单元以保存不同的数据。 因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。 因此，这种差异的差分放大使得能够获得正确的存储信息。 因此，提高了电可重写非易失性存储单元的保持性能。
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公开(公告)号：US20100290290A1
公开(公告)日：2010-11-18
申请号：US12766603
申请日：2010-04-23
申请人： Takashi KONO , Ken Matsubara , Takashi Iwase
发明人： Takashi KONO , Ken Matsubara , Takashi Iwase
摘要： A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.
摘要翻译： 提供一种非易失性半导体存储器件，其可以以低消耗电流精确地读取数据。 闪速存储器响应于时钟信号的前沿根据外部地址信号选择存储器单元，并且响应于正常读取模式下的时钟信号的前沿从存储器单元读取数据，而在 用于执行具有比正常读取模式更低的功耗的读取操作的低速读取模式，响应于时钟信号的后沿从存储器单元读取数据。 因此，由于噪声电平在时钟信号的后沿已经下降，所以即使在低速读取模式中响应于时钟信号的前沿产生噪声，也可以准确地读取数据。
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