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    Semiconductor device including single crystal silicon layer
    1.
    发明授权
    Semiconductor device including single crystal silicon layer 有权
    半导体器件包括单晶硅层

    公开(公告)号：US07772711B2

    公开(公告)日：2010-08-10

    申请号：US11430117

    申请日：2006-05-09

    申请人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaoxin Zhang

    发明人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Do-young Kim ,  Jang-yeong Kwon ,  Huaxiang Yin ,  Kyung-bae Park ,  Xiaoxin Zhang

    IPC分类号： H01L27/11

    CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/7842 ,  Y10S257/903

    摘要： A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of . The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.

    摘要翻译： 包括基板，形成在基板上的P-MOS单晶TFT的半导体器件和形成在P-MOS单晶TFT上的N-MOS单晶TFT。 P-MOS单晶TFT的源极区域和N-MOS单晶TFT的源极区域可以彼此连接。 P-MOS单晶TFT和N-MOS单晶TFT可以共用公共栅极。 此外，P-MOS单晶TFT可以包括具有（100）的晶面并且晶体方向<100的单晶硅层。 N-MOS单晶TFT可以包括与P-MOS单晶TFT的单晶硅层相同的晶体方向的单晶硅层，其拉应力大于P-MOS的单晶硅层 单晶TFT。

    Single crystal substrate and method of fabricating the same
    5.
    发明申请
    Single crystal substrate and method of fabricating the same 审中-公开
    单晶基板及其制造方法

    公开(公告)号：US20100041214A1

    公开(公告)日：2010-02-18

    申请号：US12461315

    申请日：2009-08-07

    申请人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Xiaoxin Zhang ,  Huaxiang Yin

    发明人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Xiaoxin Zhang ,  Huaxiang Yin

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02636 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02532 ,  H01L21/02686

    摘要： A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or germanium seed layer on the portion of the substrate exposed through the window; depositing a silicon or germanium material layer, which are crystallization target material layers, on the epitaxial growth silicon 6r germanium seed layer and the insulator; and crystallizing the crystallization target material layer by melting and cooling the crystallization target material layer.

    摘要翻译： 提供了高质量的单晶基板及其制造方法。 制造单晶衬底的方法包括：在衬底上形成绝缘体; 在所述绝缘体中形成窗口，所述窗口暴露所述基板的一部分; 在通过窗户暴露的衬底的部分上形成外延生长硅或锗种子层; 在外延生长硅6r锗种子层和绝缘体上沉积作为结晶靶材料层的硅或锗材料层; 并且通过熔化和冷却结晶化目标材料层来使结晶目标材料层结晶。

    Method of fabricating orientation-controlled single-crystalline wire and method of fabricating transistor having the same
    7.
    发明授权
    Method of fabricating orientation-controlled single-crystalline wire and method of fabricating transistor having the same 有权
    制造取向控制单晶线的方法及其制造具有该晶体管的晶体管的方法

    公开(公告)号：US07566364B2

    公开(公告)日：2009-07-28

    申请号：US11483586

    申请日：2006-07-11

    申请人： Wenxu Xianyu ,  Young-Soo Park ,  Takashi Noguchi ,  Hans S. Cho ,  Xiaoxin Zhang ,  Huaxiang Yin

    发明人： Wenxu Xianyu ,  Young-Soo Park ,  Takashi Noguchi ,  Hans S. Cho ,  Xiaoxin Zhang ,  Huaxiang Yin

    IPC分类号： C30B25/04

    CPC分类号： C30B29/06 ,  C30B25/005 ,  C30B29/08 ,  C30B29/60

    摘要： Provided may be a method of fabricating nanowires and a method of fabricating a transistor having the same. The method may include: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed in the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface; supplying gaseous crystal growth materials through the second apertures; and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer. The nanowires may be made of crystalline materials, e.g., Si or SiGe, and may be formed parallel to the substrate. Higher quality nanowires, whose orientation may be controlled, may be formed. A higher quality transistor may be formed on the substrate by applying a method of fabricating the nanowires.

    摘要翻译： 可以提供制造纳米线的方法和制造具有该纳米线的晶体管的方法。 该方法可以包括：在衬底上形成模板层，模板层具有第一侧表面和面向第一表面的第二侧表面; 在模板层中形成孔，孔设置在模板层中的第一侧表面和第二侧表面之间，并且在第一侧表面中具有第一孔; 形成与设置在模板层的第一侧表面中的第一孔接触的单晶材料层; 形成连接设置在所述第二侧表面中的孔的第二孔; 通过所述第二孔提供气态晶体生长材料; 以及通过从单晶材料层的晶体生长在孔中形成结晶纳米线。 纳米线可以由例如Si或SiGe的结晶材料制成，并且可以与基底平行地形成。 可以形成其取向可以被控制的更高质量的纳米线。 可以通过应用制造纳米线的方法在衬底上形成更高质量的晶体管。

    Si nanowire substrate
    8.
    发明授权
    Si nanowire substrate 有权
    Si纳米线基板

    公开(公告)号：US07714330B2

    公开(公告)日：2010-05-11

    申请号：US11889471

    申请日：2007-08-14

    申请人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

    发明人： Hans S. Cho ,  Takashi Noguchi ,  Wenxu Xianyu ,  Do-Young Kim ,  Huaxiang Yin ,  Xiaoxin Zhang

    IPC分类号： H01L29/04

    CPC分类号： H01L29/78654 ,  H01L29/0673 ,  H01L29/66772 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/814 ,  Y10S977/90 ,  Y10S977/938 ,  Y10T428/26

    摘要： A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

    摘要翻译： 具有其中在衬底上形成具有细线宽度的硅纳米线膜的结构的硅纳米线衬底，其制造方法以及使用其制造薄膜晶体管的方法。 制造硅纳米线基板的方法包括：准备基板，在基板上形成绝缘膜，在绝缘膜上形成硅膜，将绝缘膜和硅膜图形化成带状，减小线宽 通过对绝缘膜的至少一个侧面进行底切蚀刻来绝缘膜，并且通过使硅膜熔化和结晶，在绝缘膜的上表面上形成自对准硅纳米线膜。

    Semiconductor device including gate stack formed on inclined surface and method of fabricating the same
    9.
    发明申请
    Semiconductor device including gate stack formed on inclined surface and method of fabricating the same 有权
    包括在倾斜表面上形成的栅叠层的半导体器件及其制造方法

    公开(公告)号：US20100112763A1

    公开(公告)日：2010-05-06

    申请号：US12654866

    申请日：2010-01-07

    申请人： Xiaoxin Zhang ,  Wenxu Xianyu ,  Takashi Noguchi ,  Hans S. Cho ,  Huaxiang Yin

    发明人： Xiaoxin Zhang ,  Wenxu Xianyu ,  Takashi Noguchi ,  Hans S. Cho ,  Huaxiang Yin

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/82385

    摘要： A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.

    摘要翻译： 半导体器件包括晶体管。 晶体管包括具有倾斜表面的基板，从倾斜表面的下部延伸的第一上表面和从倾斜表面的上端延伸的第二上表面。 栅极堆叠结构形成在倾斜表面上并且包括栅电极。 形成在第一和第二上表面中的一个上的第一杂质区域接触栅极堆叠结构。 形成在第二上表面上的第二杂质区域接触栅堆叠结构。 第一和第二杂质区之间的通道在结晶方向上沿着倾斜表面形成。

    Semi-conductor-on-insulator structure, semiconductor devices using the same and method of manufacturing the same
    10.
    发明授权
    Semi-conductor-on-insulator structure, semiconductor devices using the same and method of manufacturing the same 有权
    半导体绝缘体上的结构，使用其的半导体器件及其制造方法

    公开(公告)号：US07557411B2

    公开(公告)日：2009-07-07

    申请号：US11397866

    申请日：2006-04-05

    申请人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Huaxiang Yin ,  Xiaoxin Zhang

    发明人： Takashi Noguchi ,  Hans S. Cho ,  Wenxu Xianyu ,  Huaxiang Yin ,  Xiaoxin Zhang

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/392

    CPC分类号： H01L29/78687 ,  H01L29/66742 ,  H01L29/78603

    摘要： Semiconductor-on-insulator (SOI) structures, semiconductor devices using the same and methods of manufacturing the same, and more particularly, to a structure with a single-crystalline (for example, germanium (x-Ge)) layer on an insulating layer, semiconductor devices using the same, and methods of manufacturing the same. The SOI structure may include a single-crystalline substrate formed of a first semiconductor material, a first insulating layer formed on the substrate and having at least one window exposing a portion of the substrate, a first epitaxial growth region formed on a surface of the substrate exposed by the window and formed of at least one of the first semiconductor material and a second semiconductor material, and a first single-crystalline layer formed on the first insulating layer and the first epitaxial growth region and formed of the second semiconductor material, and crystallized using a surface of the first epitaxial growth region as a seed layer for crystallization.

    摘要翻译： 绝缘体上半导体（SOI）结构，使用其的半导体器件及其制造方法，更具体地说，涉及在绝缘层上具有单晶（例如锗（x-Ge））层的结构 ，使用其的半导体器件及其制造方法。 SOI结构可以包括由第一半导体材料形成的单晶衬底，形成在衬底上的第一绝缘层，并且具有暴露衬底的一部分的至少一个窗口，形成在衬底表面上的第一外延生长区域 由窗口露出并由第一半导体材料和第二半导体材料中的至少一个形成，以及形成在第一绝缘层和第一外延生长区上并由第二半导体材料形成的第一单晶层，并且晶化 使用第一外延生长区域的表面作为晶种层进行结晶。