公开(公告)号：US20110254096A1

公开(公告)日：2011-10-20

申请号：US13167058

申请日：2011-06-23

申请人： Takayuki Hiraoka ,  Kuniaki Utsumi ,  Tsutomu Kojima ,  Kenji Honda

发明人： Takayuki Hiraoka ,  Kuniaki Utsumi ,  Tsutomu Kojima ,  Kenji Honda

IPC分类号： H01L29/772

CPC分类号： H01L29/0847 ,  H01L21/823418 ,  H01L27/0266 ,  H01L27/088 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device includes first and second MOSFETs corresponding to at least first power source voltage and second power source voltage lower than the first power source voltage, and non-silicide regions formed in drain portions of the first and second MOSFETs and having no silicide formed therein. The first MOSFET includes first diffusion layers formed in source/drain portions, a second diffusion layer formed below a gate portion and formed shallower than the first diffusion layer and a third diffusion layer formed with the same depth as the second diffusion layer in the non-silicide region, and the second MOSFET includes fourth diffusion layers formed in source/drain portions, a fifth diffusion layer formed below a gate portion and formed shallower than the fourth diffusion layer and a sixth diffusion layer formed shallower than the fourth diffusion layer and deeper than the fifth diffusion layer in the non-silicide region.

摘要翻译： 半导体器件包括对应于至少第一电源电压和低于第一电源电压的第二电源电压的第一和第二MOSFET，以及形成在第一和第二MOSFET的漏极部分中并且不形成在其中的硅化物的非硅化物区域 。 第一MOSFET包括形成在源极/漏极部分的第一扩散层，形成在栅极部分下方并形成为比第一扩散层浅的第二扩散层，以及形成在第一扩散层中的与第二扩散层相同深度的第三扩散层， 硅化物区域，第二MOSFET包括形成在源极/漏极部分的第四扩散层，形成在栅极部分下方并形成为比第四扩散层浅的第五扩散层和形成为比第四扩散层浅的第六扩散层， 非硅化物区域中的第五扩散层。

公开(公告)号：US20070047162A1

公开(公告)日：2007-03-01

申请号：US11511520

申请日：2006-08-29

申请人： Kentaro Watanabe ,  Koichi Sato ,  Takayuki Hiraoka

发明人： Kentaro Watanabe ,  Koichi Sato ,  Takayuki Hiraoka

IPC分类号： H02H9/00

CPC分类号： H01L27/0266

摘要： An electrostatic protection circuit including: a first power supply terminal 110; a second power supply terminal 112; an input-output terminal 111 for an external connection; a P-type MOSFET for a buffer 108 for pulling up input and output to a high-level potential; an N-type MOSFET for the buffer 107 for pulling down the input and output to a low-level potential; a rectifying element 109 connected between the first and second power supply terminals; a detector 101 for comparing the potential of the input-output terminal 111 to the potential of the first power supply terminal 110 to detect whether or not an electrostatic surge is flowing in; and controllers 105 and 106, wherein the controllers 105 and 106 control a gate potential of the N-type MOSFET 107 for the buffer when the detector 101 detects inflow of the electrostatic surge and turn off the N-type MOSFET 107 for the buffer. Discharge of the electrostatic surge is performed through a parasitic bipolar junction transistor 121 formed on the N-type MOSFET 107.

摘要翻译： 一种静电保护电路，包括：第一电源端子110; 第二电源端子112; 用于外部连接的输入 - 输出端子111; 用于缓冲器108的P型MOSFET，用于将输入和输出提升到高电平电位; 用于缓冲器107的N型MOSFET，用于将输入和输出降低到低电平电位; 连接在第一和第二电源端子之间的整流元件109; 用于将输入输出端子111的电位与第一电源端子110的电位进行比较以检测静电浪涌是否流入的检测器101; 以及控制器105和106，其中当检测器101检测到静电浪涌的流入并关闭用于缓冲器的N型MOSFET 107时，控制器105和106控制用于缓冲器的N型MOSFET 107的栅极电位。 通过形成在N型MOSFET 107上的寄生双极结型晶体管121进行静电浪涌的放电。

公开(公告)号：US6161960A

公开(公告)日：2000-12-19

申请号：US269788

申请日：1999-04-01

申请人： Takayuki Hiraoka ,  Tsuyoshi Hamawaki ,  Tatsuya Ide

发明人： Takayuki Hiraoka ,  Tsuyoshi Hamawaki ,  Tatsuya Ide

IPC分类号： B65D88/16 ,  B65D90/04 ,  B65D33/01

CPC分类号： B65D90/046 ,  B65D88/1668 ,  B65D2590/046

摘要： A container for use in bulk transporting chemical goods, grains and the like, comprises a sack body in the form of a rectangular parallelepiped prepared from a cylindrical blown film. The container has a feeding end, a discharging end and a ventilating end. Enhanced pressure-resistive strength is obtained by improving the ventilating end-mounted design so as to have a specific shape. In one embodiment, a line slit is formed through the sack body, a cylindrical film is inserted into the slit, and the sack body and the cylindrical film are bonded to each other in line along the periphery of the slit so that the bonded corner spots, of the sack body and the cylindrical film, located at both ends of the slit, has a shape of a convex curve, for example, a circular shape or a ringed shape. This bonded structure makes it possible to deconcentrate pressure applied in using and filling the container without concentrating on the corner spot to prevent generation of pinholes and sack burst of the container.

摘要翻译： PCT No.PCT / JP98 / 03804 Sec。 371日期1999年4月1日 102（e）1999年4月1日PCT PCT 1998年8月27日PCT公布。 出版物WO99 /​​ 11533 日期1999年3月11日用于散装运输化学品，谷物等的容器包括由圆柱形吹塑薄膜制成的长方体形状的袋体。 容器具有进料端，排出端和通风端。 通过改善通风端安装的设计以获得具有特定形状的增强的耐压强度。 在一个实施例中，通过袋体形成线狭缝，将圆柱形膜插入狭缝中，并且袋体和圆柱形膜沿着狭缝的周边线条彼此结合，使得粘合的角点 位于狭​​缝的两端的袋体和圆筒状薄膜具有凸曲线的形状，例如圆形或环形。 这种结合结构使得可以在使用和填充容器时施加的压力分散，而不会集中在角点上，以防止产生针孔并且破裂容器的爆裂。

公开(公告)号：US08030713B2

公开(公告)日：2011-10-04

申请号：US12401698

申请日：2009-03-11

申请人： Takayuki Hiraoka ,  Toshikazu Fukuda

发明人： Takayuki Hiraoka ,  Toshikazu Fukuda

IPC分类号： H01L27/088

CPC分类号： H01L21/823418 ,  H01L21/823412 ,  H01L27/0251 ,  H01L27/088 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/7848

摘要： A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

摘要翻译： 未形成硅锗层的硅锗非形成区域和形成有硅锗层的硅锗形成区域设置在硅芯片中，内部电路和输入/输出缓冲器布置在硅 - 锗形成区域，以及焊盘电极和静电保护元件布置在硅 - 锗非形成区域中。

公开(公告)号：US20090026493A1

公开(公告)日：2009-01-29

申请号：US12243826

申请日：2008-10-01

申请人： Takayuki Hiraoka

发明人： Takayuki Hiraoka

IPC分类号： H01L27/00

CPC分类号： H01L27/0262

摘要： An electrostatic protection circuit includes a thyristor that discharges an excess charge generated between a first power supply terminal and a second power supply terminal having a lower voltage than the first power supply terminal, a trigger device that supplies a current turning on the thyristor, and an electrostatic discharge element placed between the first power supply terminal and the second power supply terminal in parallel with thyristor and having a higher current supply capability than the trigger device at the same inter-power-terminal voltage, the electrostatic element changing to an on state in a time shorter than a turn-on time of the thyristor connected to the trigger device and at a voltage lower than a turn-on voltage of the thyristor.

摘要翻译： 静电保护电路包括：晶闸管，其对在第一电源端子和具有比第一电源端子低的电压的第二电源端子之间产生的过量电荷进行放电;提供电流导通晶闸管的触发装置，以及 静电放电元件放置在与晶闸管并联的第一电源端子和第二电源端子之间，并且在相同的功率之间电压下具有比触发器件更高的电流供应能力，静电元件变为导通状态 该时间比连接到触发装置的晶闸管的导通时间短，并且电压低于晶闸管的导通电压。

公开(公告)号：US07205611B2

公开(公告)日：2007-04-17

申请号：US10805040

申请日：2004-03-18

申请人： Atsushi Honjoh ,  Takayuki Hiraoka

发明人： Atsushi Honjoh ,  Takayuki Hiraoka

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a protection circuit protecting a semiconductor integrated circuit from electrostatic discharge, the protection circuit has a detection circuit detecting the electrostatic discharge, a trigger circuit generating a trigger signal based on the output signal of the detection circuit, and a thyristor having a PNP transistor and an NPN transistor, and operating by the trigger signal from the trigger circuit, the PNP transistor having an emitter connected to a first terminal of the semiconductor device, the NPN transistor having an emitter connected to a second terminal of the semiconductor device and a collector connected to base of the PNP transistor. The protection circuit further has a switching element controlling the connected between the PNP and NPN transistors in accordance with the output signal of the detection circuit.

摘要翻译： 半导体器件包括保护半导体集成电路免受静电放电的保护电路，保护电路具有检测静电放电的检测电路，基于检测电路的输出信号产生触发信号的触发电路以及具有 PNP晶体管和NPN晶体管，并且由来自触发电路的触发信号操作，PNP晶体管具有连接到半导体器件的第一端子的发射极，NPN晶体管具有连接到半导体器件的第二端子的发射极， 一个连接到PNP晶体管基极的集电极。 保护电路还具有根据检测电路的输出信号来控制连接在PNP和NPN晶体管之间的开关元件。

公开(公告)号：US20110051299A1

公开(公告)日：2011-03-03

申请号：US12754746

申请日：2010-04-06

申请人： Takayuki Hiraoka

发明人： Takayuki Hiraoka

IPC分类号： H02H9/00

CPC分类号： H01L27/0255 ,  H01L2224/05554

摘要： A semiconductor integrated circuit includes: an internal circuit formed on a semiconductor chip, power being supplied thereto via a first power supply wire and a second power supply wire; input and output pads that exchange an input signal or an output signal with the internal circuit; input and output cells including first electrostatic protection elements that protect the internal circuit from electrostatic discharge between the input and output pads and the first or second power supply wire; and second power supply protection elements provided adjacent to the input and output cells and including diode strings connected between the first power supply wire and the second power supply wire.

摘要翻译： 半导体集成电路包括：形成在半导体芯片上的内部电路，经由第一电源线和第二电源线供电的内部电路; 与内部电路交换输入信号或输出信号的输入和输出焊盘; 输入和输出单元包括第一静电保护元件，其保护内部电路免受输入和输出焊盘与第一或第二电源线之间的静电放电; 以及与所述输入和输出单元相邻设置并且包括连接在所述第一电源线和所述第二电源线之间的二极管串的第二电源保护元件。

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

公开(公告)号：US20090289310A1

公开(公告)日：2009-11-26

申请号：US12401698

申请日：2009-03-11

申请人： Takayuki Hiraoka ,  Toshikazu Fukuda

发明人： Takayuki Hiraoka ,  Toshikazu Fukuda

IPC分类号： H01L27/088 ,  H01L29/417 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/823412 ,  H01L27/0251 ,  H01L27/088 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/7848

摘要： A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silicon-germanium formation region, and a pad electrode and an electrostatic protection element are arranged in the silicon-germanium non-formation region.

摘要翻译： 未形成硅锗层的硅锗非形成区域和形成有硅锗层的硅 - 锗形成区域设置在硅芯片中，内部电路和输入/输出缓冲器布置在硅 - 锗形成区域，以及焊盘电极和静电保护元件布置在硅 - 锗非形成区域中。

公开(公告)号：US20080137245A1

公开(公告)日：2008-06-12

申请号：US11951269

申请日：2007-12-05

申请人： Takayuki Hiraoka

发明人： Takayuki Hiraoka

IPC分类号： H02H9/04

CPC分类号： H01L27/0255 ,  H01L23/5286 ,  H01L24/06 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

摘要： A semiconductor device is disclosed, which includes first, second and third power supply pads arranged in a peripheral area of a semiconductor chip, the second pad applied with a higher potential than the first pad, and the third pad applied with a higher potential than the second pad, first, second and third power supply wirings arranged in the peripheral area, the first wiring connected to the first pad, the second wiring connected to the second pad, and the third wiring connected to the third pad, a plurality of first electrostatic protection circuits arranged in the peripheral area and connected between the first and second wirings in correspondence to the first, second and third pads, and a plurality of second electrostatic protection circuits arranged in the peripheral area and connected between the second and third wirings in correspondence to the first, second and third pads.

摘要翻译： 公开了一种半导体器件，其包括布置在半导体芯片的周边区域中的第一，第二和第三电源焊盘，第二焊盘施加比第一焊盘更高的电位，并且施加比第一焊盘更高的电位的第三焊盘 布置在周边区域中的第二焊盘，第一，第二和第三电源布线，连接到第一焊盘的第一布线，连接到第二焊盘的第二布线和连接到第三焊盘的第三布线，多个第一静电 保护电路，布置在周边区域中，并且与第一，第二和第三焊盘相对应地连接在第一和第二布线之间，并且多个第二静电保护电路布置在周边区域中，并且连接在第二和第三布线之间，对应于 第一，第二和第三垫。