公开(公告)号：US20080212373A1

公开(公告)日：2008-09-04

申请号：US12027744

申请日：2008-02-07

申请人： Takehiro HASEGAWA ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

发明人： Takehiro HASEGAWA ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

IPC分类号： G11C16/04 ,  H01L29/788

CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

公开(公告)号：US07672164B2

公开(公告)日：2010-03-02

申请号：US12027744

申请日：2008-02-07

申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

IPC分类号： G11C16/04

CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

公开(公告)号：US07332766B2

公开(公告)日：2008-02-19

申请号：US11083156

申请日：2005-03-18

申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

公开(公告)号：US20050218460A1

公开(公告)日：2005-10-06

申请号：US11083156

申请日：2005-03-18

申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

IPC分类号： G11C16/04 ,  G11C16/02 ,  H01L21/00 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

公开(公告)号：US06943402B2

公开(公告)日：2005-09-13

申请号：US10642753

申请日：2003-08-19

申请人： Shigeru Nagasaka ,  Fumitaka Arai ,  Akira Umezawa

发明人： Shigeru Nagasaka ,  Fumitaka Arai ,  Akira Umezawa

IPC分类号： G11C16/06 ,  G11C11/00 ,  G11C16/04 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A nonvolatile semiconductor memory device includes memory cells including a first MOS transistor, and a boosting circuit including a capacitor element. The first MOS transistor includes a charge accumulation layer and a control gate formed on the charge accumulation layer with an inter-gate insulating film interposed therebetween. The capacitor element includes a first and a second semiconductor layers, a capacitor insulating film, and a third semiconductor layer. The first and second semiconductor layers are formed on a semiconductor substrate and separated from each other. The capacitor insulating film is formed on the top and side of each of the first and second semiconductor layers and on the semiconductor substrate between the first and second semiconductor layers and is made of the same material as that of the inter-gate insulating film. The third semiconductor layer is formed on the capacitor insulating film and is isolated electrically from the second semiconductor layer.

摘要翻译： 非易失性半导体存储器件包括包括第一MOS晶体管和包括电容器元件的升压电路的存储单元。 第一MOS晶体管包括电荷累积层和形成在电荷累积层上的栅极间绝缘膜之间的控制栅极。 电容器元件包括第一和第二半导体层，电容器绝缘膜和第三半导体层。 第一和第二半导体层形成在半导体衬底上并彼此分离。 电容器绝缘膜形成在第一和第二半导体层的每一个的顶部和侧面以及在第一和第二半导体层之间的半导体衬底上，并且由与栅极间绝缘膜相同的材料制成。 第三半导体层形成在电容器绝缘膜上，并与第二半导体层电隔离。

公开(公告)号：US20050253183A1

公开(公告)日：2005-11-17

申请号：US11091408

申请日：2005-03-29

申请人： Akira Umezawa ,  Fumitaka Arai

发明人： Akira Umezawa ,  Fumitaka Arai

IPC分类号： H01L29/417 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory device includes electrically rewritable memory cells formed in a cell array area of a semiconductor substrate. Each cell has spaced-apart source and drain regions, a charge storage layer overlying a channel between the source and drain, and a control gate overlying the charge storage layer. The device also includes a source line for common connection of the sources of those memory cells disposed along a word line by source-use conductors buried in mutually connected contact holes of the sources, drain-use conductors buried in contact holes of the drains of the cells, a transistor formed in a peripheral circuit area of the substrate to have a pair of source/drain regions and a gate electrode over a channel between the source/drain regions, and source/drain-use conductors buried in contact holes of the source/drain regions. Each source/drain buried conductor is longer than the drain-use buried conductor when viewing planarly.

摘要翻译： 非易失性半导体存储器件包括形成在半导体衬底的单元阵列区域中的电可重写存储单元。 每个单元具有间隔开的源极和漏极区域，覆盖源极和漏极之间的沟道的电荷存储层以及覆盖电荷存储层的控制栅极。 该装置还包括源极线，用于通过埋在源极的相互连接的接触孔中的源极使用导体沿着字线设置的那些存储器单元的源的公共连接，埋入在源极的漏极的接触孔中的漏极使用导体 形成在基板的外围电路区域中的晶体管，以在源极/漏极区域之间的沟道上方具有一对源极/漏极区域和栅电极，以及埋在源极的接触孔中的源极/漏极导体 /漏区。 当平面观察时，每个源极/漏极掩埋导体比漏极使用的埋入导体长。

公开(公告)号：US07245530B2

公开(公告)日：2007-07-17

申请号：US11111878

申请日：2005-04-22

申请人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

发明人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

IPC分类号： G11C16/04

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115

摘要： A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，位线，源极线，字线和选择栅极线。 每个存储单元包括具有浮置栅极和控制栅极的第一MOS晶体管和具有堆叠栅极的第二MOS晶体管，所述堆叠栅极包括形成在第一栅极电极上方的第一栅电极和第二栅电极，并且其漏极连接到 第一MOS晶体管的源极。 每个位线在同一列中电连接第一MOS晶体管的漏极。 每个字线将第一MOS晶体管的控制栅极连接在同一行。 每个选择栅极线将第二MOS晶体管的第二栅极电连接在同一行中，并与第二栅极电隔离。

公开(公告)号：US20050237808A1

公开(公告)日：2005-10-27

申请号：US11111878

申请日：2005-04-22

申请人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

发明人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

IPC分类号： G11C16/04 ,  G11C11/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115

摘要： A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，位线，源极线，字线和选择栅极线。 每个存储单元包括具有浮置栅极和控制栅极的第一MOS晶体管和具有堆叠栅极的第二MOS晶体管，所述堆叠栅极包括形成在第一栅极电极上方的第一栅电极和第二栅电极，并且其漏极连接到 第一MOS晶体管的源极。 每个位线在同一列中电连接第一MOS晶体管的漏极。 每个字线将第一MOS晶体管的控制栅极连接在同一行。 每个选择栅极线将第二MOS晶体管的第二栅极电连接在同一行中，并与第二栅极电隔离。

公开(公告)号：US07312503B2

公开(公告)日：2007-12-25

申请号：US10753324

申请日：2004-01-09

申请人： Akira Umezawa ,  Takehiro Hasegawa

发明人： Akira Umezawa ,  Takehiro Hasegawa

IPC分类号： H01L29/76 ,  H01L31/062

CPC分类号： H01L27/11526 ,  G11C16/0433 ,  G11C16/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11546 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.

摘要翻译： 半导体存储器件包括多个存储单元，多个局部位线，全局位线，第一开关元件和保持电路。 存储单元包括第一和第二MOS晶体管。 第一MOS晶体管具有电荷累积层和控制栅极。 第二MOS晶体管的电流路径的一端连接到第一MOS晶体管的电流路径的一端。 局部位线连接第一MOS晶体管的电流路径的另一端。 第一个开关元件在本地位线和全局位线之间建立连接。 保持电路连接到全局位线，并保存要写入存储单元的数据。

公开(公告)号：US08432744B2

公开(公告)日：2013-04-30

申请号：US13053839

申请日：2011-03-22

申请人： Akira Umezawa ,  Noriyasu Kumazaki ,  Daisuke Arizono ,  Mami Kakoi

发明人： Akira Umezawa ,  Noriyasu Kumazaki ,  Daisuke Arizono ,  Mami Kakoi

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/30 ,  G11C16/14

摘要： A semiconductor storage device according to an embodiment includes multiple memory cells which electrically rewrite data, a well control circuit which outputs an erasure voltage to be applied to a well through an output terminal, a first pump circuit which outputs a voltage set by boosting an input voltage to the output terminal, a second pump circuit which outputs a voltage set by boosting the input voltage to the output terminal and outputs a voltage higher than an output voltage of the first pump circuit, a pump switching detecting circuit which outputs an assist signal to perform a boosting operation on at least one of the first pump circuit and the second pump circuit and an erase pulse control circuit which sets target voltages of the first pump circuit and the second pump circuit, on the basis of setting values to set a target voltage of the erasure voltage.

摘要翻译： 根据实施例的半导体存储装置包括电重写数据的多个存储单元，输出通过输出端施加到阱的擦除电压的阱控制电路，第一泵电路，其通过升压输入端输出设定的电压 输出端子的电压;第二泵电路，其通过将输入电压升压到输出端子而输出电压，并输出高于第一泵电路的输出电压的电压;泵切换检测电路，其将辅助信号输出到 在第一泵电路和第二泵电路中的至少一个上执行升压操作，以及擦除脉冲控制电路，其基于设定值设定第一泵电路和第二泵电路的目标电压，以设定目标电压 的擦除电压。