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    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate
    1.
    发明授权
    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate 失效
    具有包括浮动栅极和控制栅极的堆叠栅极的半导体集成电路器件

    公开(公告)号：US07672164B2

    公开(公告)日：2010-03-02

    申请号：US12027744

    申请日：2008-02-07

    申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

    摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

    摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate
    2.
    发明授权
    Semiconductor integrated circuit device with a stacked gate including a floating gate and a control gate 失效
    具有包括浮动栅极和控制栅极的堆叠栅极的半导体集成电路器件

    公开(公告)号：US07332766B2

    公开(公告)日：2008-02-19

    申请号：US11083156

    申请日：2005-03-18

    申请人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    发明人： Takehiro Hasegawa ,  Akira Umezawa ,  Koji Sakui ,  Fumitaka Arai ,  Ryo Mitani

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/11524 ,  G11C11/005 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

    摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.

    摘要翻译： 半导体集成电路器件包括第一和第二非易失性半导体存储器。 第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。 第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。 第二存储器具有第三选择晶体管和第二存储单元晶体管。 第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。 第一和第二栅极绝缘膜具有相同的膜厚度。 第一和第二浮栅具有相同的膜厚度。 第一和第二栅极间绝缘膜具有相同的膜厚度。 第一和第二控制栅具有相同的膜厚度。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5615163A

    公开(公告)日：1997-03-25

    申请号：US598706

    申请日：1996-02-08

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory device
    7.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5038191A

    公开(公告)日：1991-08-06

    申请号：US486842

    申请日：1990-03-01

    申请人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Koji Sakui ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/41 ,  G11C11/401 ,  G11C11/404 ,  G11C11/411 ,  G11C11/412 ,  H01L21/331 ,  H01L21/8229 ,  H01L27/102 ,  H01L29/73 ,  H01L29/732

    CPC分类号： G11C11/4113 ,  G11C11/404 ,  G11C11/412

    摘要： A semiconductor memory device comprises a memory array including a plurality of memory cells arranged in a matrix form, a plurality of word lines arranged in column and a plurality of bit lines arranged in row. Each memory cell includes a bipolar transistor in which a collector-emitter voltage is controlled so that the polarity of a base current changes is changed in accordance with an increase in a base-emitter voltage, and a switching element, provided between the base of the bipolar transistor and an associated bit line and controllable by an associated word line. A switch circuit is provided for applying a collector voltage to the collector of the bipolar transistor smaller in a second state where an associated one of the memory cells is holding data than in a second state where the associated memory cell is accessible for data reading and data writing.

    摘要翻译： 半导体存储器件包括存储器阵列，其包括以矩阵形式布置的多个存储器单元，排列成列的多个字线和排成行的多个位线。 每个存储单元包括双极晶体管，其中控制集电极 - 发射极电压，使得基极电流变化的极性根据基极 - 发射极电压的增加而改变，并且开关元件设置在基极 双极晶体管和相关联的位线，并且可由相关联的字线控制。 提供一种开关电路，用于在第二状态下将集电极电压施加到双极晶体管的集电极，在第二状态下，相关联的一个存储单元保持数据而不是相关联的存储单元可访问用于数据读取和数据的第二状态 写作。

    Semiconductor memory device
    9.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5517457A

    公开(公告)日：1996-05-14

    申请号：US360289

    申请日：1994-12-21

    申请人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    发明人： Koji Sakui ,  Hiroshi Nakamura ,  Tomoharu Tanaka ,  Masaki Momodomi ,  Fujio Masuoka ,  Takehiro Hasegawa

    IPC分类号： G11C16/06 ,  G11C5/02 ,  G11C11/401 ,  G11C11/407 ,  G11C16/04 ,  G11C16/08 ,  G11C17/00 ,  G11C29/00 ,  G11C29/04 ,  H01L29/78 ,  G11C13/00

    CPC分类号： G11C29/80 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/08 ,  G11C5/025

    摘要： An NAND cell type EEPROM comprising a memory cell array wherein an NAND cell unit having a plurality of electrically rewritable memory cells is connected in series, and the NAND cell is formed on a semiconductor substrate in a matrix array, a plurality of control gate lines CG each provided to cross an NAND cell group of the same row, bit lines BL each provided to cross the NAND cell group of the same column, wherein driver circuit are provided at both sides of the memory cell array in a ratio of one to two NAND cell units so as to drive the control gate lines CG, the plurality of the control gate lines CG, provided to cross the NAND cell unit of the even row, is connected to the left driver circuit, and the plurality of the control gate lines CG, provided to cross the NAND cell unit of the odd row, is connected to the right driver circuit.

    摘要翻译： 包括存储单元阵列的NAND单元型EEPROM，其中具有多个电可重写存储单元的NAND单元单元串联连接，NAND单元形成在矩阵阵列的半导体基板上，多个控制栅线CG 每个被提供以跨过同一行的NAND单元组，每个位线BL被提供以跨过同一列的NAND单元组，其中驱动电路以一到两个NAND的比率设置在存储单元阵列的两侧 单元单元以驱动控制栅极线CG，设置为跨越偶数行的NAND单元单元的多个控制栅极线CG连接到左侧驱动电路，并且多个控制栅极线CG 被提供以跨越奇数行的NAND单元单元连接到右驱动器电路。

    Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same
    10.
    发明申请
    Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same 失效
    具有MOS晶体管的半导体存储器件，各自包括浮动栅极和控制栅极，以及包括其的存储卡

    公开(公告)号：US20050237808A1

    公开(公告)日：2005-10-27

    申请号：US11111878

    申请日：2005-04-22

    申请人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

    发明人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

    IPC分类号： G11C16/04 ,  G11C11/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115

    摘要： A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

    摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，位线，源极线，字线和选择栅极线。 每个存储单元包括具有浮置栅极和控制栅极的第一MOS晶体管和具有堆叠栅极的第二MOS晶体管，所述堆叠栅极包括形成在第一栅极电极上方的第一栅电极和第二栅电极，并且其漏极连接到 第一MOS晶体管的源极。 每个位线在同一列中电连接第一MOS晶体管的漏极。 每个字线将第一MOS晶体管的控制栅极连接在同一行。 每个选择栅极线将第二MOS晶体管的第二栅极电连接在同一行中，并与第二栅极电隔离。