公开(公告)号：US6064607A

公开(公告)日：2000-05-16

申请号：US177484

申请日：1998-10-23

申请人： Takeo Miki ,  Mikio Asakura ,  Satoshi Kawasaki

发明人： Takeo Miki ,  Mikio Asakura ,  Satoshi Kawasaki

IPC分类号： G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C8/10

摘要： Each of first and second program circuits includes a determination node, first to fourth fuses, first to fourth N channel MOS transistors, and first to fourth supply lines. The first to fourth N channel MOS transistors receive first to fourth row address predecode signals, respectively. The first N channel MOS transistor included in the first program circuit and the first N channel MOS transistor included in the second program circuit are arranged adjacent to each other. The first supply line provides a first row address predecode signal to the gate of these two N channel MOS transistors. The same applies for the second to fourth N channel MOS transistors and the second to fourth supply lines. Accordingly, the interconnection capacitance of the row address predecode signal line can be reduced. Also, the size of the transistor driving the row address predecode signal and the transistors in the program circuit can be reduced to allow a smaller layout area for the entire chip.

摘要翻译： 第一和第二编程电路中的每一个包括确定节点，第一至第四保险丝，第一至第四N沟道MOS晶体管和第一至第四电源线。 第一至第四N沟道MOS晶体管分别接收第一至第四行地址预解码信号。 包括在第一编程电路中的第一N沟道MOS晶体管和包括在第二编程电路中的第一N沟道MOS晶体管彼此相邻布置。 第一电源线为这两个N沟道MOS晶体管的栅极提供第一行地址预解码信号。 同样适用于第二至第四N沟道MOS晶体管和第二至第四供电线。 因此，可以减少行地址预解码信号线的互连电容。 此外，可以减小驱动行地址预解码信号的晶体管的尺寸和程序电路中的晶体管的尺寸，以允许整个芯片的布局面积较小。

公开(公告)号：US07032066B2

公开(公告)日：2006-04-18

申请号：US09956346

申请日：2001-09-20

申请人： Takeo Miki ,  Mikio Asakura ,  Takeshi Hamamoto

发明人： Takeo Miki ,  Mikio Asakura ,  Takeshi Hamamoto

IPC分类号： G11C7/10

CPC分类号： G11C5/06 ,  G11C7/10 ,  G11C7/1066 ,  G11C11/4093

摘要： In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

公开(公告)号：US06207998B1

公开(公告)日：2001-03-27

申请号：US09329290

申请日：1999-06-10

申请人： Satoshi Kawasaki ,  Mikio Asakura ,  Kenji Tokami

发明人： Satoshi Kawasaki ,  Mikio Asakura ,  Kenji Tokami

IPC分类号： H01L2976

CPC分类号： H01L29/66181 ,  G11C11/4097 ,  H01L27/0629 ,  H01L27/10897

摘要： An MOS capacitor is provided in the proximity of the boundary between a P well and an N well formed of a bottom N well and an N well. Accordingly, the proximity of the boundary corresponding to the so-called dead space can be used effectively.

摘要翻译： 在由P阱和N阱形成的N阱和N阱之间的边界附近提供MOS电容器。 因此，可以有效地利用与所谓的死空间对应的边界的接近度。

公开(公告)号：US06551846B1

公开(公告)日：2003-04-22

申请号：US09642751

申请日：2000-08-18

申请人： Kiyohiro Furutani ,  Mikio Asakura ,  Tetsuo Katoh

发明人： Kiyohiro Furutani ,  Mikio Asakura ,  Tetsuo Katoh

IPC分类号： G01R3126

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.

摘要翻译： 测试信号发生电路在测试模式操作中从经由地址终端提供的少量信号产生内部测试控制信号。 根据测试控制信号，设置来自地址缓冲器的内部行地址信号位的值，而具有测试控制功能的行相关控制电路根据测试控制来控制行选择电路和位线外围电路的操作 信号。 多个字线被同时驱动到选择状态，并且在短时间段内根据少量的控制信号执行加速度测试。 存储单元电容器和字线之间施加的电压应力可以用少量的控制信号加速。

公开(公告)号：US06377512B1

公开(公告)日：2002-04-23

申请号：US09666133

申请日：2000-09-20

申请人： Takeshi Hamamoto ,  Takuya Ariki ,  Mikio Asakura ,  Takayuki Nishiyama

发明人： Takeshi Hamamoto ,  Takuya Ariki ,  Mikio Asakura ,  Takayuki Nishiyama

IPC分类号： G11C818

CPC分类号： G11C8/12 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072

摘要： Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

摘要翻译： 数据总线与焊盘一一对应地布置。 这些数据总线被共同布置成多个存储器阵列。 读数据驱动器根据字配置选择性地被有效地切换以切换存储器阵列和数据总线之间的连接。

公开(公告)号：US06269038B1

公开(公告)日：2001-07-31

申请号：US09556290

申请日：2000-04-24

申请人： Takashi Itou ,  Yasuhiko Tsukikawa ,  Kengo Aritomi ,  Mikio Asakura

发明人： Takashi Itou ,  Yasuhiko Tsukikawa ,  Kengo Aritomi ,  Mikio Asakura

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.

摘要翻译： 提供了测试模式判定电路，其在第一WCBR周期中通过激活测试模式输入信号来响应地址键，并且在第二WCBR周期中激活的测试模式输入信号通过选择性地激活测试模式信号来响应地址键 。 测试模式判定电路除了测试模式信号被激活之外，还激活另一个测试模式信号。 因此，DRAM几乎不会错误地进入测试模式，并且还能够同时进入多个测试模式。

公开(公告)号：US6157588A

公开(公告)日：2000-12-05

申请号：US229343

申请日：1999-01-13

申请人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

发明人： Yasuhiro Matsumoto ,  Mikio Asakura ,  Takeshi Hamamoto ,  Kei Hamade

IPC分类号： G11C11/407 ,  G11C7/18 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02

CPC分类号： G11C7/18 ,  G11C11/4097

摘要： First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

摘要翻译： 第一和第二全局输入/输出线在第一和第二主块之间扭转。 第一主块中的第一和第二SD信号线分别布置成与第一和第二全局输入/输出线相邻。 第二主块中的第一和第二SD信号线分别布置成与第二和第一全局输入/输出线相邻。 为第一或第二SD信号线提供的SD信号对第一和第二全局输入/输出线施加相同的噪声，使得在第一和第二全局输入/输出线之间基本上消除了噪声的影响。 因此，全球输入/输出线路具有更高的抗噪声能力，而不会增加布局面积。

公开(公告)号：US5999464A

公开(公告)日：1999-12-07

申请号：US58885

申请日：1998-04-13

申请人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

发明人： Hideto Hidaka ,  Mikio Asakura ,  Kiyohiro Furutani ,  Tetsuo Kato

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/14 ,  G11C29/24

CPC分类号： G11C29/24

摘要： A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.

公开(公告)号：US5978299A

公开(公告)日：1999-11-02

申请号：US222793

申请日：1998-12-30

申请人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

发明人： Kyoji Yamasaki ,  Tadaaki Yamauchi ,  Mikio Asakura

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/34

CPC分类号： G11C5/147

摘要： A semiconductor memory device includes a memory cell array, peripheral circuits including a column decoder for connecting a word line, and a VDC circuit for peripherals, for generating an internal power supply voltage based on an external power supply voltage. VDC circuit for peripherals supplies the internal power supply voltage to peripheral circuits including the column decoder, other than the sense amplifier, output buffer and internal initial stage. The supplying capability of the VDC circuit for peripherals is increased in response to a VDCE signal which is output from a clock generation circuit when column decoder is activated. Therefore, even when power consumption in the peripheral circuit is increased as the column decoder is activated, sufficient power can be supplied to the peripheral circuit.

公开(公告)号：US5970507A

公开(公告)日：1999-10-19

申请号：US676963

申请日：1996-07-08

申请人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

发明人： Tetsuo Kato ,  Kiyohiro Furutani ,  Hideto Hidaka ,  Mikio Asakura

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/409 ,  G06F12/00

CPC分类号： G11C11/406

摘要： In a semiconductor memory device, a self refresh cycle program circuit is provided and a refresh operation is conducted in accordance with one of the refresh cycles programmed in the refresh-cycle program circuit. The refresh cycle of the self-refresh mode is selected from a plurality of refresh-cycle types. A plurality of refresh modes allows a refresh cycle to be selected from a plurality of refresh-cycle types in accordance with a selected refresh mode.

摘要翻译： 在半导体存储器件中，提供自刷新周期程序电路，并且根据在刷新周期程序电路中编程的刷新周期之一进行刷新操作。 从多个刷新周期类型中选择自刷新模式的刷新周期。 多个刷新模式允许根据所选择的刷新模式从多个刷新周期类型中选择刷新周期。