公开(公告)号：US08395434B1

公开(公告)日：2013-03-12

申请号：US13253784

申请日：2011-10-05

申请人： Qui Vi Nguyen ,  Takuya Ariki ,  Jongmin Park

发明人： Qui Vi Nguyen ,  Takuya Ariki ,  Jongmin Park

IPC分类号： H03L5/00

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/12

摘要： A level shifter circuit is presented that can apply a negative voltage level to non-selected blocks while still being able to drive a high positive level when selected. An exemplary embodiment presents a negative level shifter that is not susceptible to low voltage pfet breakdown. This allows for a high voltage level shifter (transfer gate) that can drive a negative level for unselected blocks and, when enabled for a selected block, can still drive a positive high voltage level. By using a pair of low voltage PMOS device whose n-wells share the same level as other PMOS transistors in the design, layout area can be minimized. The gates of this pair of PMOSs are connected to VSS, thereby preventing these low voltage PMOS devices from thin oxide breakdown.

摘要翻译： 提出了一种电平移位器电路，其可以对未选择的块施加负电压电平，同时当选择时仍能够驱动高电平。 一个示例性实施例提出了不易受低电压pfet击穿的负电平移位器。 这允许可以为未选择的块驱动负电平的高电压电平移位器（传输门），并且当对于所选择的块使能时，仍然可以驱动正的高电压电平。 通过使用一对低压PMOS器件，其n阱在设计中与其他PMOS晶体管共享相同的电平，布局面积可以最小化。 这对PMOS的栅极连接到VSS，从而防止这些低电压PMOS器件的薄氧化物破坏。

公开(公告)号：US07881122B2

公开(公告)日：2011-02-01

申请号：US12334573

申请日：2008-12-15

申请人： Takuya Ariki

发明人： Takuya Ariki

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/30 ,  G11C8/08 ,  G11C16/14

摘要： Provided is a discharge circuit. The discharge circuit for discharging two positive and negative high voltages after an erase operation of a non-volatile memory includes: a negative high voltage side discharge unit flowing constant current from a supply voltage to a negative high voltage node of the non-volatile memory to discharge the negative high voltage node; and a positive high voltage side discharge unit flowing constant current from a positive high voltage node of the non-volatile memory to a ground voltage to discharge the positive high voltage node, the positive high voltage side discharge unit simultaneously operating with the negative high voltage side discharge unit, wherein values of the constant currents flowing from the positive and negative high voltage side discharge units are approximately equal.

摘要翻译： 提供放电电路。 在非易失性存储器的擦除操作之后用于放电两个正和负高电压的放电电路包括：将恒定电流从电源电压流向非易失性存储器的负高压节点的负高压侧放电单元， 放电负高压节点; 以及将恒定电流从非易失性存储器的正高压节点流向地电压的正高压侧放电单元，以使正高压节点放电，正高压侧放电单元与负高压侧同时工作 放电单元，其中从正极和负极高压侧放电单元流出的恒定电流的值近似相等。

公开(公告)号：US5815032A

公开(公告)日：1998-09-29

申请号：US694440

申请日：1996-08-12

申请人： Takuya Ariki ,  Hiroshi Akamatsu ,  Shigeru Mori

发明人： Takuya Ariki ,  Hiroshi Akamatsu ,  Shigeru Mori

IPC分类号： G11C11/409 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/408 ,  H01L21/822 ,  H01L27/04 ,  H03K3/01

CPC分类号： G11C5/146 ,  G11C11/4074

摘要： A detect circuit receives a write enable signal, a column address strobe signal and an output control signal to predetect a mode in which data is input from an input/output terminal. While a substrate potential generation circuit normally operates, a substrate potential holding circuit also operates when the detect circuit detects the mode in which data is input, so that biasing capability of a substrate potential generating portion is increased before the data is actually input from the input/output terminal.

摘要翻译： 检测电路接收写使能信号，列地址选通信号和输出控制信号，以预测从输入/输出端输入数据的模式。 当衬底电位产生电路正常工作时，当检测电路检测到数据输入的模式时，衬底电位保持电路也工作，使得在从输入实际输入数据之前增加衬底电位产生部分的偏置能力 /输出端子。

公开(公告)号：US08076911B2

公开(公告)日：2011-12-13

申请号：US12144769

申请日：2008-06-24

申请人： Takuya Ariki

发明人： Takuya Ariki

IPC分类号： G05F1/70 ,  G05F1/40

CPC分类号： G05F1/56 ,  G11C5/147 ,  G11C16/30

摘要： A voltage regulator includes a voltage regulator unit configured to output a step voltage and a damping resistance switching unit coupled between a load and an output node of the voltage regulator and configured to select an optimal damping resistance value based on a required load capacity.

摘要翻译： 电压调节器包括被配置为输出阶梯电压的调压器单元和耦合在所述电压调节器的负载和输出节点之间并被配置为基于所需负载能力选择最佳阻尼电阻值的阻尼电阻切换单元。

公开(公告)号：US20090179694A1

公开(公告)日：2009-07-16

申请号：US12334573

申请日：2008-12-15

申请人： Takuya ARIKI

发明人： Takuya ARIKI

IPC分类号： G05F1/10

CPC分类号： G11C16/30 ,  G11C8/08 ,  G11C16/14

摘要： Provided is a discharge circuit. The discharge circuit for discharging two positive and negative high voltages after an erase operation of a non-volatile memory includes: a negative high voltage side discharge unit flowing constant current from a supply voltage to a negative high voltage node of the non-volatile memory to discharge the negative high voltage node; and a positive high voltage side discharge unit flowing constant current from a positive high voltage node of the non-volatile memory to a ground voltage to discharge the positive high voltage node, the positive high voltage side discharge unit simultaneously operating with the negative high voltage side discharge unit, wherein values of the constant currents flowing from the positive and negative high voltage side discharge units are approximately equal.

摘要翻译： 提供放电电路。 在非易失性存储器的擦除操作之后用于放电两个正和负高电压的放电电路包括：将恒定电流从电源电压流向非易失性存储器的负高压节点的负高压侧放电单元， 放电负高压节点; 以及将恒定电流从非易失性存储器的正高压节点流向地电压的正高压侧放电单元，以使正高压节点放电，正高压侧放电单元与负高压侧同时工作 放电单元，其中从正极和负极高压侧放电单元流出的恒定电流的值近似相等。

公开(公告)号：US06727584B2

公开(公告)日：2004-04-27

申请号：US10264025

申请日：2002-10-04

申请人： Hiroto Tokutome ,  Takuya Ariki

发明人： Hiroto Tokutome ,  Takuya Ariki

IPC分类号： H01L2334

CPC分类号： H05K1/181 ,  H01L23/5382 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H05K1/0292 ,  H05K3/225 ,  H05K2201/10689 ,  H05K2203/049 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of electrical wires are provided on a rear surface of a semiconductor module substrate having a structure that it is possible to mount a repair chip having a long lead and a repair chip having a normal lead in an overlaying manner and that it is possible to provide either repair chip or repair chip, which correspond to a plurality of bare chips, respectively. Thereby, it is possible to obtain a semiconductor module capable of repairing in a case where any bare chip becomes defective or even in a case where any combination of bare chips becomes defective.

摘要翻译： 多个电线设置在半导体模块基板的后表面上，该半导体模块基板具有可以以重叠的方式安装具有长引线的修复芯片和具有正常引线的修复芯片的结构，并且可以 提供分别对应于多个裸芯片的修复芯片或修复芯片。 因此，可以获得在任何裸芯片变得缺陷的情况下甚至在裸芯片的任何组合变得缺陷的情况下能够修复的半导体模块。

公开(公告)号：US06535438B2

公开(公告)日：2003-03-18

申请号：US09955020

申请日：2001-09-19

申请人： Takuya Ariki

发明人： Takuya Ariki

IPC分类号： G11C700

CPC分类号： G11C29/785 ,  G11C29/846

摘要： A determination circuit included in a memory device determines availability to replace a defective cell within the memory device with a spare memory cell. An output signal indicating a result of determination is generated. Thus, even after the memory device is packaged, it can be easily determined whether a repair is possible by detecting the level of the output signal.

摘要翻译： 包括在存储器装置中的确定电路确定用备用存储器单元替换存储器件内的有缺陷单元的可用性。 产生表示确定结果的输出信号。 因此，即使在存储器件被封装之后，也可以通过检测输出信号的电平来容易地确定是否可以进行修理。

公开(公告)号：US06166989A

公开(公告)日：2000-12-26

申请号：US261153

申请日：1999-03-03

申请人： Takeshi Hamamoto ,  Takuya Ariki ,  Mikio Asakura ,  Takayuki Nishiyama

发明人： Takeshi Hamamoto ,  Takuya Ariki ,  Mikio Asakura ,  Takayuki Nishiyama

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C8/12 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1072

摘要： Data buses are arranged in a one-to-one correspondence to pads. These data buses are arranged in common to a plurality of memory arrays. A read data driver is rendered active selectively according to a word configuration to switch equivalently the connection between a memory array and a data bus.

公开(公告)号：US07710793B2

公开(公告)日：2010-05-04

申请号：US12191537

申请日：2008-08-14

申请人： Yuichiro Nakagaki ,  Takuya Ariki

发明人： Yuichiro Nakagaki ,  Takuya Ariki

IPC分类号： G11C7/06

CPC分类号： G11C16/30 ,  G11C8/08

摘要： Provided are a write voltage generating circuit of a non-volatile memory cell and a write voltage generating method. The write voltage generating circuit includes a voltage generating unit providing a preliminary write voltage at a level below a defined target level, a voltage sensing unit receiving the preliminary write voltage and a reference signal, and in response to a comparison between the preliminary write voltage and the reference signal generating a start signal, and a switching unit generating and applying a write voltage derived from the preliminary write voltage at a writeable level to a non-volatile memory cell during the write operation in response to the start signal, wherein the writeable level is less than the target level.

摘要翻译： 提供了非易失性存储单元的写入电压产生电路和写入电压产生方法。 写入电压产生电路包括：电压产生单元，其提供低于定义的目标电平的初级写入电压;接收初步写入电压的电压感测单元和参考信号;以及响应于初步写入电压和 所述参考信号产生起始信号，以及切换单元，响应于所述起始信号，在所述写入操作期间，将写入电平的写入电压从写入电平产生并施加到非易失性存储器单元，其中所述可写入电平 小于目标水平。

公开(公告)号：US20090046518A1

公开(公告)日：2009-02-19

申请号：US12191537

申请日：2008-08-14

申请人： Yuichiro NAKAGAKI ,  Takuya ARIKI

发明人： Yuichiro NAKAGAKI ,  Takuya ARIKI

IPC分类号： G11C7/00

CPC分类号： G11C16/30 ,  G11C8/08

摘要： Provided are a write voltage generating circuit of a non-volatile memory cell and a write voltage generating method. The write voltage generating circuit includes a voltage generating unit providing a preliminary write voltage at a level below a defined target level, a voltage sensing unit receiving the preliminary write voltage and a reference signal, and in response to a comparison between the preliminary write voltage and the reference signal generating a start signal, and a switching unit generating and applying a write voltage derived from the preliminary write voltage at a writeable level to a non-volatile memory cell during the write operation in response to the start signal, wherein the writeable level is less than the target level.

摘要翻译： 提供了非易失性存储单元的写入电压产生电路和写入电压产生方法。 写入电压产生电路包括：电压产生单元，其提供低于定义的目标电平的初级写入电压;接收初步写入电压的电压感测单元和参考信号;以及响应于初步写入电压和 所述参考信号产生起始信号，以及切换单元，响应于所述起始信号，在所述写入操作期间，将写入电平的写入电压从写入电平产生并施加到非易失性存储器单元，其中所述可写入电平 小于目标水平。