公开(公告)号：US20090236722A1

公开(公告)日：2009-09-24

申请号：US12400390

申请日：2009-03-09

申请人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura ,  Takuya Futatsuyama

发明人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura ,  Takuya Futatsuyama

IPC分类号： H01L23/48 ,  H01L23/12

CPC分类号： H01L23/5388 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device.

摘要翻译： 半导体存储卡包括具有外部形状的布线板，其中切口部分设置在第一长边缘处。 布线板的第二表面包括沿着除了第一长边缘的切口部分之外的部分设置的连接焊盘。 存储器件安装在布线板的第二表面上。 存储装置包括沿着布线板的第一长边缘附近的长边定位布置的电极焊盘，并且一边设置成与连接焊盘的布置位置相对应。 控制器装置堆叠在存储器件上。

公开(公告)号：US20080316696A1

公开(公告)日：2008-12-25

申请号：US11767801

申请日：2007-06-25

申请人： Taku NISHIYAMA ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku NISHIYAMA ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H05K7/02

CPC分类号： H01L27/105 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/11517 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

摘要翻译： 半导体存储器件设置有包括元件安装部分和连接焊盘的布线板。 多个半导体存储元件堆叠在布线板的元件安装部分上。 下侧的半导体存储元件的厚度大于上侧的半导体存储元件的厚度。 半导体存储元件通过金属线电连接到布线板的连接焊盘。

公开(公告)号：US08395268B2

公开(公告)日：2013-03-12

申请号：US13172571

申请日：2011-06-29

申请人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H01L23/48

CPC分类号： G11C5/063 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads; metallic wires for electrically connecting the electrode pads of the plurality of semiconductor elements included in the first and second element groups to the connection pads of the wiring board; and a sealing resin layer formed on the wiring board so as to seal the first and second element groups together with the metallic wires.

摘要翻译： 半导体存储器件包括：布线板，包括元件安装部分和连接焊盘; 包括多个半导体元件的第一元件组，每个半导体元件具有沿着所述半导体元件的一个外侧布置的电极焊盘，所述多个半导体元件以所述布线板的元件安装部分的方式逐层地分层， 半导体元件面向相同方向，电极焊盘露出; 包括多个半导体元件的第二元件组，每个半导体元件具有沿着所述半导体元件的一个外侧布置的电极焊盘，所述多个半导体元件以半导体元件的衬垫布置面朝向所述第一元件组逐级分层 在与第一元件组相同的方向上，并且电极焊盘被暴露，第二元件组被设置为沿着电极焊盘的布置方向偏离第一元件组; 金属线，用于将包括在第一和第二元件组中的多个半导体元件的电极焊盘电连接到布线板的连接焊盘; 以及密封树脂层，其形成在所述布线板上，以与所述金属线一起密封所述第一和第二元件组。

公开(公告)号：US08274141B2

公开(公告)日：2012-09-25

申请号：US12400390

申请日：2009-03-09

申请人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura ,  Takuya Futatsuyama

发明人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura ,  Takuya Futatsuyama

IPC分类号： H01L23/02

CPC分类号： H01L23/5388 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device.

摘要翻译： 半导体存储卡包括具有外部形状的布线板，其中切口部分设置在第一长边缘处。 布线板的第二表面包括沿着除了第一长边缘的切口部分之外的部分设置的连接焊盘。 存储器件安装在布线板的第二表面上。 存储装置包括沿着布线板的第一长边缘附近的长边定位布置的电极焊盘，并且一边设置成与连接焊盘的布置位置相对应。 控制器装置堆叠在存储器件上。

公开(公告)号：US08064206B2

公开(公告)日：2011-11-22

申请号：US13009947

申请日：2011-01-20

申请人： Taku Nishiyama ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku Nishiyama ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H05K1/14

CPC分类号： H01L27/105 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/11517 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

公开(公告)号：US08004071B2

公开(公告)日：2011-08-23

申请号：US12343921

申请日：2008-12-24

申请人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/12

CPC分类号： G11C5/063 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads;metallic wires for electrically connecting the electrode pads of the plurality of semiconductor elements included in the first and second element groups to the connection pads of the wiring board; and a sealing resin layer formed on the wiring board so as to seal the first and second element groups together with the metallic wires.

摘要翻译： 半导体存储器件包括：布线板，包括元件安装部分和连接焊盘; 包括多个半导体元件的第一元件组，每个半导体元件具有沿着所述半导体元件的一个外侧布置的电极焊盘，所述多个半导体元件以所述布线板的元件安装部分的方式逐层地分层， 半导体元件面向相同方向，电极焊盘露出; 包括多个半导体元件的第二元件组，每个半导体元件具有沿着所述半导体元件的一个外侧布置的电极焊盘，所述多个半导体元件以半导体元件的衬垫布置面朝向所述第一元件组逐级分层 在与第一元件组相同的方向上，并且电极焊盘被暴露，第二元件组被设置为沿着电极焊盘的布置方向偏离第一元件组; 金属线，用于将包括在第一和第二元件组中的多个半导体元件的电极焊盘电连接到布线板的连接焊盘; 以及密封树脂层，其形成在所述布线板上，以与所述金属线一起密封所述第一和第二元件组。

公开(公告)号：US20090166829A1

公开(公告)日：2009-07-02

申请号：US12343921

申请日：2008-12-24

申请人： Taku NISHIYAMA ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku NISHIYAMA ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H01L23/495

CPC分类号： G11C5/063 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element group in an arrangement direction of the electrode pads; metallic wires for electrically connecting the electrode pads of the plurality of semiconductor elements included in the first and second element groups to the connection pads of the wiring board; and a sealing resin layer formed on the wiring board so as to seal the first and second element groups together with the metallic wires.

摘要翻译： 半导体存储器件包括：布线板，包括元件安装部分和连接焊盘; 包括多个半导体元件的第一元件组，每个半导体元件具有沿着所述半导体元件的一个外侧布置的电极焊盘，所述多个半导体元件以所述布线板的元件安装部分的方式逐层地分层， 半导体元件面向相同方向，电极焊盘露出; 包括多个半导体元件的第二元件组，每个半导体元件具有沿着所述半导体元件的一个外侧布置的电极焊盘，所述多个半导体元件以半导体元件的衬垫布置面朝向所述第一元件组逐级分层 在与第一元件组相同的方向上，并且电极焊盘被暴露，第二元件组被设置为沿着电极焊盘的布置方向偏离第一元件组; 金属线，用于将包括在第一和第二元件组中的多个半导体元件的电极焊盘电连接到布线板的连接焊盘; 以及密封树脂层，其形成在所述布线板上，以与所述金属线一起密封所述第一和第二元件组。

公开(公告)号：US07898813B2

公开(公告)日：2011-03-01

申请号：US11767801

申请日：2007-06-25

申请人： Taku Nishiyama ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku Nishiyama ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H05K1/14

CPC分类号： H01L27/105 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/11517 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

摘要翻译： 半导体存储器件设置有包括元件安装部分和连接焊盘的布线板。 多个半导体存储元件堆叠在布线板的元件安装部分上。 下侧的半导体存储元件的厚度大于上侧的半导体存储元件的厚度。 半导体存储元件通过金属线电连接到布线板的连接焊盘。

公开(公告)号：US20110110053A1

公开(公告)日：2011-05-12

申请号：US13009947

申请日：2011-01-20

申请人： Taku Nishiyama ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

发明人： Taku Nishiyama ,  Kiyokazu Okada ,  Yoriyasu Ando ,  Tetsuya Yamamoto ,  Naohisa Okumura

IPC分类号： H05K1/18

CPC分类号： H01L27/105 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/11517 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.

摘要翻译： 半导体存储器件设置有包括元件安装部分和连接焊盘的布线板。 多个半导体存储元件堆叠在布线板的元件安装部分上。 下侧的半导体存储元件的厚度大于上侧的半导体存储元件的厚度。 半导体存储元件通过金属线电连接到布线板的连接焊盘。

公开(公告)号：US07732908B2

公开(公告)日：2010-06-08

申请号：US12238983

申请日：2008-09-26

申请人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Kiyokazu Okada

发明人： Taku Nishiyama ,  Tetsuya Yamamoto ,  Kiyokazu Okada

IPC分类号： H01L23/02

CPC分类号： H01L25/18 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/0105 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.

摘要翻译： 构成第一元件组的多个半导体元件在布线板上以阶梯状形式堆叠。 构成第二元件组的多个半导体元件朝向与第一元件组的阶梯方向相反的方向在第一元件组上以阶梯状形状堆叠。 半导体元件通过金属线电连接到布线板的连接焊盘。 在构成第二元件组的多个半导体元件中，最下半导体元件的厚度大于其它半导体元件的厚度。