公开(公告)号：US5589423A

公开(公告)日：1996-12-31

申请号：US317045

申请日：1994-10-03

申请人： Ted R. White ,  Ting-Chen Hsu ,  Bradley M. Somero ,  Mark A. Chonko ,  Jung-Hui Lin

发明人： Ted R. White ,  Ting-Chen Hsu ,  Bradley M. Somero ,  Mark A. Chonko ,  Jung-Hui Lin

IPC分类号： H01L21/8234 ,  H01L27/02 ,  H01L21/70 ,  H01L21/306 ,  H01L21/465 ,  H01L27/00

CPC分类号： H01L29/8605 ,  H01L21/823443 ,  H01L27/0251 ,  H01L29/665

摘要： A process for the fabrication of a non-silicided region in an integrated circuit includes the fabrication of a silicide blocking layer (24, 46, 54, 92, 112). In one embodiment, a field transistor (80) is formed by depositing a silicide blocking layer (84) overlying a field gate electrode (70) and source and drain regions (76, 78). A carbonaceous mask (86) is formed on the silicide blocking layer (84) overlying the field transistor (80). A partial etching process is performed to remove a portion of the silicide blocking layer (84) exposed by the carbonaceous mask (86). Then, the carbonaceous mask (86) is removed and the etching process is continued to completely remove portions of the silicide blocking layer (84) not originally protected by the carbonaceous mask (86). The etching process forms a silicide blocking layer (92) overlying the field transistor (80) and sidewall (94) adjacent to an MOS gate electrode (68).

摘要翻译： 在集成电路中制造非硅化区域的方法包括制造硅化物阻挡层（24,46,54,92,112）。 在一个实施例中，通过沉积覆盖场栅极（70）和源极和漏极区（76,78）的硅化物阻挡层（84）来形成场晶体管（80）。 在覆盖场晶体管（80）的硅化物阻挡层（84）上形成碳质掩模（86）。 执行部分蚀刻工艺以去除由碳质掩模（86）暴露的硅化物阻挡层（84）的一部分。 然后，除去碳质掩模（86），并继续蚀刻处理，以完全去除最初不被碳质掩模（86）保护的硅化物阻挡层（84）的部分。 蚀刻工艺形成覆盖场MOS晶体管（80）和与MOS栅电极（68）相邻的侧壁（94）的硅化物阻挡层（92）。

公开(公告)号：US5918147A

公开(公告)日：1999-06-29

申请号：US413021

申请日：1995-03-29

申请人： Stanley M. Filipiak ,  Ted R. White ,  T. P. Ong ,  Jung-Hui Lin ,  Wayne M. Paulson ,  Bernard J. Roman

发明人： Stanley M. Filipiak ,  Ted R. White ,  T. P. Ong ,  Jung-Hui Lin ,  Wayne M. Paulson ,  Bernard J. Roman

IPC分类号： G03F7/11 ,  H01L21/027 ,  H01L21/285 ,  H01L21/316 ,  H01L21/318 ,  H01L21/3213

CPC分类号： H01L21/28512 ,  H01L21/0276 ,  H01L21/31604 ,  H01L21/3185 ,  H01L21/32133

摘要： Antireflective layers (54, 86, and 109) have been developed that have discrete portions (541, 542, 861, 862, 863, 1091, and 1092). The discrete portions (541, 542, 861, 862, 863, 1091, and 1092) allow the antireflective layers (54, 86, and 109) to be used in many instances where using a single layer of uniform composition would be difficult or impossible. Alternatively, a single antireflective layer with a continuously graded composition can be used.

摘要翻译： 已经开发了具有离散部分（541,542,861,862,863,1091和1092）的抗反射层（54,86和109）。 离散部分（541,542,861,862,863,1091和1092）允许在许多情况下使用抗反射层（54,86和109），其中使用均匀组成的单层将是困难的或不可能的 。 或者，可以使用具有连续渐变组成的单个抗反射层。

公开(公告)号：US07032271B2

公开(公告)日：2006-04-25

申请号：US10815741

申请日：2004-04-02

申请人： Jung-Hui Lin

发明人： Jung-Hui Lin

IPC分类号： E05F5/06

CPC分类号： E05F5/08 ,  E05F5/02 ,  E05Y2201/212 ,  E05Y2201/264 ,  E05Y2201/474 ,  Y10T16/61 ,  Y10T16/625 ,  Y10T16/629

摘要： A noise control device for a steel door includes a buffer, a shock-absorbing member, a stopping member, or only includes a colliding member. The noise control device is installed at any location of a steel door and a casting where noise may be generated when the steel door is closed or opened. The buffer consists of a cylinder, a lower sponge, a coil spring, a rod, and an upper sponge and possibly a colliding member. The buffer can be mainly installed on a deadbolt groove of the casing. The shock-absorbing member may be fixed on the steel door or the casing for reducing sound. The stopping member is fixed on the steel door to face the outer end of the buffer. The noise control device can reduce noise generated in opening and closing as much as possible and preventing the both from disfiguring or denting.

摘要翻译： 用于钢门的噪声控制装置包括缓冲器，减震构件，止动构件，或仅包括碰撞构件。 噪音控制装置安装在钢门和铸钢件的任何位置，当钢门关闭或打开时可能产生噪音。 缓冲器由圆筒，下海绵，螺旋弹簧，杆和上海绵以及可能的碰撞构件组成。 缓冲器可以主要安装在壳体的螺栓槽上。 减震构件可以固定在钢门或壳体上以减少声音。 止动件固定在钢门上以面对缓冲器的外端。 噪声控制装置可以尽可能地减少打开和关闭中产生的噪声，并且防止两者的损坏或凹陷。

公开(公告)号：US5651858A

公开(公告)日：1997-07-29

申请号：US690192

申请日：1996-07-26

申请人： Jung-Hui Lin

发明人： Jung-Hui Lin

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/306

CPC分类号： H01L21/3065

摘要： A method for forming a tapered opening in a silicon substrate uses NF.sub.3 and HBr. The NF.sub.3 /HBr plasma etch allows both a good taper profile, 85.degree. to 60.degree., as well as a good etch rate, approximately 2500 to 3000 .ANG./minute. Although not limited to a particular trench size, the present method is well suited for forming openings smaller than 0.45 .mu.m.

摘要翻译： 在硅衬底中形成锥形开口的方法使用NF3和HBr。 NF3 / HBr等离子体蚀刻允许85°至60°的良好锥形轮廓以及良好的蚀刻速率，大约2500至3000 ANGSTROM /分钟。 虽然不限于特定的沟槽尺寸，但本方法非常适用于形成小于0.45μm的开口。

公开(公告)号：US5677831A

公开(公告)日：1997-10-14

申请号：US619337

申请日：1996-03-21

申请人： Jung-Hui Lin

发明人： Jung-Hui Lin

IPC分类号： H02J9/06 ,  H02M3/335

CPC分类号： H02J9/066

摘要： An uninterrupted power supply system including a square wave oscillator, a square wave drive, a negative wave drive, a first bridge drive, a second bridge drive, a bridge circuit, a R/C low pass filter, an overload protection circuit, a high-voltage generator, and a full-wave rectifier, wherein the bridge circuit consists of pairs of oxide metal field effect transistors (insulated-gate semiconductors) respectively connected by bridging for the conversion of DC power supply into AC power supply; the high-voltage generator and the bridge circuit are mounted on an expansion card so that the output power of the system can be expanded by installing additional expansion cards.

摘要翻译： 一种不间断电源系统，包括方波振荡器，方波驱动器，负波驱动器，第一桥驱动器，第二桥驱动器，桥电路，R / C低通滤波器，过载保护电路，高 电压发生器和全波整流器，其中桥电路由分别通过桥接连接用于将DC电源转换成AC电源的氧化金属场效应晶体管（绝缘栅半导体）组成; 高压发生器和桥接电路安装在扩展卡上，以便可以通过安装附加的扩展卡来扩展系统的输出功率。

公开(公告)号：US5061647A

公开(公告)日：1991-10-29

申请号：US597946

申请日：1990-10-12

申请人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

发明人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/7836

摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.

摘要翻译： 一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。 可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。 根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。 第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。 在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。 工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。 工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。 第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。

公开(公告)号：US20050217072A1

公开(公告)日：2005-10-06

申请号：US10815741

申请日：2004-04-02

申请人： Jung-Hui Lin

发明人： Jung-Hui Lin

IPC分类号： E05F5/02 ,  E05F5/06 ,  E05F5/08

CPC分类号： E05F5/08 ,  E05F5/02 ,  E05Y2201/212 ,  E05Y2201/264 ,  E05Y2201/474 ,  Y10T16/61 ,  Y10T16/625 ,  Y10T16/629

摘要： A noise control device for a steel door includes a buffer, a shock-absorbing member, a stopping member, or only includes a colliding member. The noise control device is installed at any location of a steel door and a casting where noise may be generated when the steel door is closed or opened. The buffer consists of a cylinder, a lower sponge, a coil spring, a rod, and an upper sponge and possibly a colliding member. The buffer can be mainly installed on a deadbolt groove of the casing. The shock-absorbing member may be fixed on the steel door or the casing for reducing sound. The stopping member is fixed on the steel door to face the outer end of the buffer. The noise control device can reduce noise generated in opening and closing as much as possible and preventing the both from disfiguring or denting.

摘要翻译： 用于钢门的噪声控制装置包括缓冲器，减震构件，止动构件，或仅包括碰撞构件。 噪音控制装置安装在钢门和铸钢件的任何位置，当钢门关闭或打开时可能产生噪音。 缓冲器由圆筒，下海绵，螺旋弹簧，杆和上海绵以及可能的碰撞构件组成。 缓冲器可以主要安装在壳体的螺栓槽上。 减震构件可以固定在钢门或壳体上以减少声音。 止动件固定在钢门上以面对缓冲器的外端。 噪声控制装置可以尽可能地减少打开和关闭中产生的噪声，并且防止两者的损坏或凹陷。

公开(公告)号：US5538922A

公开(公告)日：1996-07-23

申请号：US378990

申请日：1995-01-25

申请人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

IPC分类号： H01L21/60 ,  H01L21/46

CPC分类号： H01L21/76897 ,  Y10S148/02 ,  Y10S438/97

摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

摘要翻译： 接触形成在半导体器件（10）中，与底层的形貌或间距无关。 在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。 在绝缘层上沉积蚀刻停止层（20）。 在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。 从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。 绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。 取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

公开(公告)号：US5219793A

公开(公告)日：1993-06-15

申请号：US709554

申请日：1991-06-03

申请人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

发明人： Kent J. Cooper ,  Jung-Hui Lin ,  Scott S. Roth ,  Bernard J. Roman ,  Carlos A. Mazure ,  Bich-Yen Nguyen ,  Wayne J. Ray

IPC分类号： H01L21/60

CPC分类号： H01L21/76897 ,  Y10S148/02 ,  Y10S438/97

摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

摘要翻译： 接触形成在半导体器件（10）中，与底层的形貌或间距无关。 在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。 在绝缘层上沉积蚀刻停止层（20）。 在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。 从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。 绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。 取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

公开(公告)号：US5210435A

公开(公告)日：1993-05-11

申请号：US745652

申请日：1991-08-16

申请人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

发明人： Scott S. Roth ,  Carlos A. Mazure ,  Kent J. Cooper ,  Wayne J. Ray ,  Michael P. Woo ,  Jung-Hui Lin

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/7836

摘要： A semiconductor device and process wherein an ITLDD device (60) is formed having an inverse-T (IT) transistor gate with a variable work function (.PHI.) across the gate. The variable work function is attained by depositing a work function adjusting layer onto the thin gate extensions of the IT-gate. In accordance with one embodiment of the invention, a semiconductor substrate (10) of a first conductivity type is provided having a gate dielectric layer (12) formed thereon. First and second lightly doped regions (36, 37) of a second conductivity type are formed in the substrate which are spaced apart by a channel region (38). An IT-gate electrode (48) is formed on the gate dielectric layer overlying the first and second lightly doped regions and the channel region. The IT-gate has a relatively thick central section (32) and relatively thin lateral extensions (50) projecting from the central portion along the gate dielectric layer. A work function adjusting layer (46) overlies and is in intimate contact with at least the lateral extensions of the IT-gate. The presence of the work function adjusting layer changes the electrical characteristics of the extensions relative to the central section of the IT-gate. Heavily doped source and drain regions (52, 53) of the second conductivity type are formed in the substrate adjacent to the first and second lightly doped regions and aligned to the edge of the gate extensions.

摘要翻译： 一种半导体器件和工艺，其中ITLDD器件（60）形成为具有跨越栅极的具有可变功函数（PHI）的逆T（IT）晶体管栅极。 可变功函数是通过将工作功能调整层沉积到IT门的薄门延伸上来实现的。 根据本发明的一个实施例，提供具有形成在其上的栅介电层（12）的第一导电类型的半导体衬底（10）。 第二导电类型的第一和第二轻掺杂区域（36,37）形成在衬底中，其被沟道区域（38）隔开。 在覆盖第一和第二轻掺杂区域和沟道区域的栅极电介质层上形成IT栅电极（48）。 IT门具有相对较厚的中心部分（32）和相对较薄的横向延伸部分（50），从中心部分沿着栅极介电层突出。 工作功能调整层（46）覆盖至少与IT门的侧向延伸部紧密接触。 工作功能调整层的存在改变了延伸部分相对于IT门的中心部分的电气特性。 第二导电类型的重掺杂源极和漏极区域（52,53）形成在与第一和第二轻掺杂区域相邻的衬底中，并且与栅极延伸部分的边缘对准。