公开(公告)号：US20140016415A1

公开(公告)日：2014-01-16

申请号：US13546553

申请日：2012-07-11

申请人： Teruhiko Kamei ,  Cuong Trinh ,  Atsushi Inoue ,  Toshiyuki Takahashi

发明人： Teruhiko Kamei ,  Cuong Trinh ,  Atsushi Inoue ,  Toshiyuki Takahashi

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： A non-volatile storage system that performs a multi-stage programming process to program non-volatile storage to a set of data threshold voltage distributions. The multi-stage programming process includes performing a first stage of the multi-stage programming process to change threshold voltages of at least a subset of the non-volatile storage elements from an erased distribution to one or more intermediate distributions, performing an intermediate stage of the multi-stage programming process to change threshold voltages of at least some of the non-volatile storage elements to appropriate distributions of the data threshold voltage distributions, and performing a later stage of the multi-stage programming process, after performing the intermediate stage of the multi-stage programming process, to tighten only a subset of the data threshold voltage distributions.

摘要翻译： 执行多级编程处理以将非易失性存储器编程为一组数据阈值电压分布的非易失性存储系统。 多级编程过程包括执行多阶段编程过程的第一阶段，以将非易失性存储元件的至少一个子集的阈值电压从擦除分布改变到一个或多个中间分布，执行中间阶段 所述多级编程处理将所述非易失性存储元件中的至少一些的阈值电压改变为所述数据阈值电压分布的适当分布，以及在执行所述多级编程过程的后期阶段之后，执行所述多级编程处理的中间级 多级编程过程，仅收紧数据阈值电压分布的子集。

公开(公告)号：US09053819B2

公开(公告)日：2015-06-09

申请号：US13546553

申请日：2012-07-11

申请人： Teruhiko Kamei ,  Cuong Trinh ,  Atsushi Inoue ,  Toshiyuki Takahashi

发明人： Teruhiko Kamei ,  Cuong Trinh ,  Atsushi Inoue ,  Toshiyuki Takahashi

IPC分类号： G11C11/00 ,  G11C11/56 ,  G11C16/34

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： A non-volatile storage system that performs a multi-stage programming process to program non-volatile storage to a set of data threshold voltage distributions. The multi-stage programming process includes performing a first stage of the multi-stage programming process to change threshold voltages of at least a subset of the non-volatile storage elements from an erased distribution to one or more intermediate distributions, performing an intermediate stage of the multi-stage programming process to change threshold voltages of at least some of the non-volatile storage elements to appropriate distributions of the data threshold voltage distributions, and performing a later stage of the multi-stage programming process, after performing the intermediate stage of the multi-stage programming process, to tighten only a subset of the data threshold voltage distributions.

摘要翻译： 执行多级编程处理以将非易失性存储器编程为一组数据阈值电压分布的非易失性存储系统。 多级编程过程包括执行多阶段编程过程的第一阶段，以将非易失性存储元件的至少一个子集的阈值电压从擦除分布改变到一个或多个中间分布，执行中间阶段 所述多级编程处理将所述非易失性存储元件中的至少一些的阈值电压改变为所述数据阈值电压分布的适当分布，以及在执行所述多级编程过程的后期阶段之后，执行所述多级编程处理的中间级 多级编程过程，仅收紧数据阈值电压分布的子集。

公开(公告)号：US20210212952A1

公开(公告)日：2021-07-15

申请号：US17143330

申请日：2021-01-07

申请人： Cuong Trinh

发明人： Cuong Trinh

IPC分类号： A61K9/48 ,  A61K9/00 ,  A61K31/485

摘要： The invention is a method for pain relief due to rheumatoid arthritis, dermatitis, Crone's disease, fibromyalgia and multiple sclerosis. It comprises a single dose of LDN-α, a biphasic formulation of naltrexone, C20H23NO4, taken daily. Proportions of LDN-α components may be varied over a range so as to achieve a desired level of naltrexone in the blood for a period of 19 to 27 hours.

公开(公告)号：US5057712A

公开(公告)日：1991-10-15

申请号：US414312

申请日：1989-09-29

申请人： Cuong Trinh ,  Vincent K. Z. Win ,  Behzad Nouban ,  Andrew K. Chan

发明人： Cuong Trinh ,  Vincent K. Z. Win ,  Behzad Nouban ,  Andrew K. Chan

IPC分类号： H03K5/1534 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17704 ,  H03K19/17784 ,  H03K5/1534

摘要： An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the PAL such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.

摘要翻译： 公开了一种用于PAL电路的改进的地址转换检测器。 本发明在转移检测信号（TDS）总线上提供预定的逻辑输出，用于在PAL的输入焊盘上转换输入地址。 TDS总线用于触发在PAL上控制读出放大器和锁存块的phi发生器，使电路保持在低功率待机模式。 检测器包括用于缓冲地址输入以提供第一信号的第一反相器，用于反转第一信号以提供第二信号的第二反相器和用于在TDS总线上提供预定逻辑电平一段时间之后的第二反相器 第一信号和第二信号已经改变状态。

公开(公告)号：US20130105881A1

公开(公告)日：2013-05-02

申请号：US13646500

申请日：2012-10-05

申请人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

发明人： James K. Kai ,  Vinod R. Purayath ,  George Matamis ,  Nima Mokhlesi ,  Cuong Trinh

IPC分类号： H01L29/788 ,  H01L21/762 ,  H01L21/336

CPC分类号： H01L27/11519 ,  H01L27/11524 ,  H01L29/42332 ,  H01L29/66825

摘要： A non-volatile memory fabrication process includes the formation of a complete memory cell layer stack before isolation region formation. The memory cell layer stack includes an additional place holding control gate layer. After forming the layer stack columns, the additional control gate layer will be incorporated between an overlying control gate layer and underlying intermediate dielectric layer. The additional control gate layer is self-aligned to isolation regions between columns while the overlying control gate layer is etched into lines for contact to the additional control gate layer. In one embodiment, the placeholder control gate layer facilitates a contact point to the overlying control gate layer such that contact between the control gate layers and the charge storage layer is not required for select gate formation.

摘要翻译： 非易失性存储器制造工艺包括在形成隔离区之前形成完整的存储单元层堆叠。 存储单元层堆叠包括附加位置保持控制栅层。 在形成层堆叠列之后，附加的控制栅层将被并入在覆盖的控制栅极层和下面的中间介质层之间。 附加控制栅极层与柱之间的隔离区域自对准，同时将覆盖的控制栅极层蚀刻成用于与附加控制栅极层接触的线。 在一个实施例中，占位符控制栅极层有助于与上覆控制栅极层的接触点，使得选择栅极形成不需要控制栅极层与电荷存储层之间的接触。

公开(公告)号：US20090135646A1

公开(公告)日：2009-05-28

申请号：US11945120

申请日：2007-11-26

申请人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

发明人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5631 ,  G11C2211/5634

摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.

摘要翻译： 存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。 该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的 设置在存储设备外面。 在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。 该技术可以用于例如确定一组存储元件的阈值电压分布。 在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

公开(公告)号：US5136186A

公开(公告)日：1992-08-04

申请号：US752733

申请日：1991-08-30

申请人： Cuong Trinh ,  Alex Shubat

发明人： Cuong Trinh ,  Alex Shubat

IPC分类号： H03K19/003 ,  H03K19/177

CPC分类号： H03K19/00361 ,  H03K19/17708 ,  H03K19/17712

摘要： Dummy circuitry, including a dummy input buffer, associated lines, and an additional row in the PLD array, provides an additional input to the PLD to keep the voltage on the bit line low until the correct input signal has fully propagated through the working input buffer and associated lines, thereby preventing a voltage glitch.

摘要翻译： 包含虚拟输入缓冲器，相关线路和PLD阵列中的附加行的虚拟电路为PLD提供了额外的输入，以将位线上的电压保持在低电平，直到正确的输入信号完全传播通过工作输入缓冲器 和相关联的线，从而防止电压毛刺。

公开(公告)号：US5532623A

公开(公告)日：1996-07-02

申请号：US330211

申请日：1994-10-21

申请人： Manik Advani ,  Cuong Trinh

发明人： Manik Advani ,  Cuong Trinh

IPC分类号： G11C7/06 ,  G11C16/28 ,  G11C29/02 ,  G11C29/50 ,  G01R19/00

CPC分类号： G11C29/026 ,  G11C16/28 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C7/062 ,  G11C16/04 ,  G11C2029/5002 ,  G11C2029/5006

摘要： A sense amplifier includes: a pull-down device which contains a reference cell which is structurally identical to the PLD cells being sensed; and a pull-up device connected to form a current mirror which causes a saturation current of the pull-up device to be zero or greater than the current through the sensed cell. The pull-down device has a saturation current which tracks the current through the sensed cell. When current flows through the sensed cell, saturation current through the pull-up device exceeds the saturation current through the pull-down device, and an output node is pulled up. When no current flows through the sensed cell, no current flow through the pull-up device, and the pull-down device pulls the output node down. As a result, the sense amplifier exhibits a variable trip point which tracks variations cause by changes in device fabrication process, temperature, and power supply voltage. The reference cell in the sense amplifier conducts a current only during sensing, and therefore consumes no standby power.

摘要翻译： 读出放大器包括：下拉装置，其包含与被感测的PLD单元结构相同的参考单元; 以及连接以形成电流镜的上拉装置，其使得上拉装置的饱和电流为零或大于通过感测单元的电流。 下拉装置具有饱和电流，其跟踪通过感测单元的电流。 当电流流经感测单元时，通过上拉装置的饱和电流超过下拉装置的饱和电流，输出节点被拉高。 当没有电流流经感测单元时，没有电流流过上拉装置，下拉装置将输出节点向下拉。 结果，感测放大器表现出可变跳变点，其跟踪由器件制造工艺，温度和电源电压变化引起的变化。 读出放大器中的参考单元仅在感测期间导通电流，因此不需要备用电源。

公开(公告)号：US20120167100A1

公开(公告)日：2012-06-28

申请号：US12978001

申请日：2010-12-23

申请人： Yan Li ,  Alon Marcu ,  Cynthia Hsu ,  Grishma Shah ,  Cuong Trinh ,  Mehrdad Mofidi

发明人： Yan Li ,  Alon Marcu ,  Cynthia Hsu ,  Grishma Shah ,  Cuong Trinh ,  Mehrdad Mofidi

IPC分类号： G06F9/46 ,  G06F3/00

CPC分类号： G11C16/22 ,  G11C11/5621 ,  G11C16/102 ,  G11C16/26

摘要： An external controller has greater control over control circuitry on a memory die in a non-volatile storage system. The external controller can issue a manual suspend command on a communication path which is constantly monitored by the control circuitry. In response, the control circuitry suspends a task immediately, with essentially no delay, or at a next acceptable point in the task. The external controller similarly has the ability to issue a manual resume command, which can be provided on the communication path when that path has a ready status. The control circuitry can also automatically suspend and resume a task. The external controller can cause a task to be suspended by issuing an illegal read command. The external controller can cause a suspended program task to be aborted by issuing a new program command.

摘要翻译： 外部控制器对非易失性存储系统中的存储芯片上的控制电路具有更大的控制。 外部控制器可以在由控制电路不断监视的通信路径上发出手动挂起命令。 作为响应，控制电路基本上没有延迟或在任务的下一个可接受的点处立即暂停任务。 外部控制器类似地具有发出手动恢复命令的能力，当该路径具有就绪状态时，可以在通信路径上提供手动恢复命令。 控制电路还可以自动挂起和恢复任务。 外部控制器可能会通过发出非法读取命令来暂停任务。 通过发出新的程序命令，外部控制器可以导致暂停的程序任务中止。

公开(公告)号：US07613045B2

公开(公告)日：2009-11-03

申请号：US11945120

申请日：2007-11-26

申请人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

发明人： Mark Murin ,  Mark Shlick ,  Menahem Lasser ,  Cuong Trinh

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/26 ,  G11C2211/5631 ,  G11C2211/5634

摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.

摘要翻译： 存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。 该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的 设置在存储设备外面。 在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。 该技术可以用于例如确定一组存储元件的阈值电压分布。 在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。