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公开(公告)号：US07342283B2
公开(公告)日：2008-03-11
申请号：US11370038
申请日：2006-03-08
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/42364 , H01L29/42368 , H01L29/7824
摘要： An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.
摘要翻译： 本发明的目的是提供一种半导体器件，其能够在确保包括多个相互排列的多个MOS晶体管的半导体器件的每个MOS晶体管的漏极和源极之间的击穿电压的同时，减小器件面积 ，具有不同类型的通道电导率。 半导体器件包括半导体衬底，掩埋氧化物膜和半导体层，此外，半导体层具有形成MOS晶体管的岛状半导体层，MOS晶体管具有源极区域和漏极区域 位于源极区域的外围的岛状半导体层，形成有MOS晶体管的岛状半导体层，MOS晶体管具有漏极区域和位于漏极区域的周围的源极区域， 将前述岛状半导体层与半导体层的其他部分隔离的隔离沟槽，将后述的岛状半导体层与半导体层的其他部分隔离的隔离沟槽和电位为 固定在电路中的最低电位，这防止晶体管之间发生电干扰。
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公开(公告)号：US20070075393A1
公开(公告)日：2007-04-05
申请号：US11488154
申请日：2006-07-18
IPC分类号： H01L23/58
CPC分类号： H01L29/7824 , H01L29/0696 , H01L29/1095 , H01L29/4238
摘要： In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.
摘要翻译： 在形成在绝缘体上硅（SOI）衬底上的高电压P沟道MOS晶体管中，P + +型源极区域（8），N型体区域（4）和 一个N + +体接触扩散区域（10）被P + +型漏极区域（9）和P型漂移区域（5）围绕。 形成与N型体区域（4）的端部重叠的栅电极（7）。 N型体区域（4）的端部具有栅极电极（7）和P + +型源极区域（8）彼此不相邻的部分。
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公开(公告)号：US20060255406A1
公开(公告)日：2006-11-16
申请号：US11370038
申请日：2006-03-08
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76264 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/42364 , H01L29/42368 , H01L29/7824
摘要： An object of the present invention is to provide a semiconductor device which enables to reduce the device area, while securing the breakdown voltage between the drain and the source of each MOS transistor for the semiconductor device including plural MOS transistors, which are arrayed adjacently each other, with different types of channel conductivity. The semiconductor device includes a semiconductor substrate, a buried oxide film and a semiconductor layer, and furthermore the semiconductor layer has an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a source region, and a drain region that is positioned in the periphery of the source region, an island-like semiconductor layer, in which a MOS transistor is formed, the MOS transistor has a drain region, and a source region is that is positioned in the periphery of the drain region, an isolation trench which isolates the former island-like semiconductor layer from other portions of the semiconductor layer, an isolation trench which isolates the latter island-like semiconductor layer from other portions of the semiconductor layer, and a buffer region, in which the electric potential is fixed to the lowest electric potential in a circuit, which prevents an electrical interference occurred between transistors.
摘要翻译： 本发明的目的是提供一种半导体器件，其能够在确保包括多个相互排列的多个MOS晶体管的半导体器件的每个MOS晶体管的漏极和源极之间的击穿电压的同时，减小器件面积 ，具有不同类型的通道电导率。 半导体器件包括半导体衬底，掩埋氧化物膜和半导体层，此外，半导体层具有形成MOS晶体管的岛状半导体层，MOS晶体管具有源极区域和漏极区域 位于源极区域周围的岛状半导体层，形成有MOS晶体管的岛状半导体层，MOS晶体管具有漏极区域，源极区域位于漏极区域的周围， 将前述岛状半导体层与半导体层的其他部分隔离的隔离沟槽，将后述的岛状半导体层与半导体层的其他部分隔离的隔离沟槽和缓冲区域，其中电位 被固定在电路中的最低电位，这防止晶体管之间发生电干扰。
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4.发明授权公开(公告)号：US07973361B2
公开(公告)日：2011-07-05
申请号：US11362116
申请日：2006-02-27
IPC分类号： H01L31/113
CPC分类号： H01L29/0878 , H01L27/1203 , H01L29/063 , H01L29/0847 , H01L29/0886 , H01L29/1083 , H01L29/42364 , H01L29/66659 , H01L29/66681 , H01L29/66772 , H01L29/7824 , H01L29/7835 , H01L29/78621 , H01L29/78654
摘要： A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.
摘要翻译： 使用包括支撑衬底，绝缘膜和有源层的SOI衬底形成高耐压电压半导体器件。 高击穿电压半导体器件包括在有源层上形成的N型阱区和P型漏极偏移区，形成在阱区上的P型源极区，形成在漏极偏置上的P型漏极区 形成在至少位于有源层的源极区域和漏极偏移区域之间的区域中的栅极绝缘膜以及形成在栅极绝缘膜上的栅电极。 该器件还包括形成在漏极偏移区域下面的N型深阱区域。 用于形成深阱区域的N型杂质的浓度峰位于比用于形成漏极偏移区域的P型杂质的浓度峰值更深的位置。
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公开(公告)号：US07323747B2
公开(公告)日：2008-01-29
申请号：US11488154
申请日：2006-07-18
IPC分类号： H01L29/49
CPC分类号： H01L29/7824 , H01L29/0696 , H01L29/1095 , H01L29/4238
摘要： In a high voltage P-channel MOS transistor formed on a silicon-on-insulator (SOI) substrate, a P+-type source region (8), an N-type body region (4) and an N+-body contact diffusion region (10) are surrounded by a P+-type drain region (9) and a P-type drift region (5). A gate electrode (7) is formed to overlap the end portion of the N-type body region (4). The end portion of the N-type body region (4) has a portion in which the gate electrode (7) and the P+-type source region (8) are not adjacent to each other.
摘要翻译： 在形成在绝缘体上硅（SOI）衬底上的高电压P沟道MOS晶体管中，P + +型源极区域（8），N型体区域（4）和 一个N + +体接触扩散区域（10）被P + +型漏极区域（9）和P型漂移区域（5）围绕。 形成与N型体区域（4）的端部重叠的栅电极（7）。 N型体区域（4）的端部具有栅极电极（7）和P + +型源极区域（8）彼此不相邻的部分。
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6.发明申请公开(公告)号：US20060220130A1
公开(公告)日：2006-10-05
申请号：US11362116
申请日：2006-02-27
IPC分类号： H01L27/12
CPC分类号： H01L29/0878 , H01L27/1203 , H01L29/063 , H01L29/0847 , H01L29/0886 , H01L29/1083 , H01L29/42364 , H01L29/66659 , H01L29/66681 , H01L29/66772 , H01L29/7824 , H01L29/7835 , H01L29/78621 , H01L29/78654
摘要： A high breakdown voltage semiconductor device is formed using an SOI substrate comprising a support substrate, an insulating film, and an active layer. The high breakdown voltage semiconductor device comprises an N-type well region and a P-type drain offset region formed on the active layer, a P-type source region formed on the well region, a P-type drain region formed on the drain offset region, a gate insulating film formed in at least a region interposed between the source region and the drain offset region of the active layer, and a gate electrode formed on the gate insulating film. The device further comprises an N-type deep well region formed under the drain offset region. A concentration peak of N-type impurity for formation of the deep well region is located deeper than a concentration peak of P-type impurity for formation of the drain offset region.
摘要翻译： 使用包括支撑衬底，绝缘膜和有源层的SOI衬底形成高耐压电压半导体器件。 高击穿电压半导体器件包括在有源层上形成的N型阱区和P型漏极偏移区，形成在阱区上的P型源极区，形成在漏极偏置上的P型漏极区 形成在至少位于有源层的源极区域和漏极偏移区域之间的区域中的栅极绝缘膜以及形成在栅极绝缘膜上的栅电极。 该器件还包括形成在漏极偏移区域下面的N型深阱区域。 用于形成深阱区域的N型杂质的浓度峰位于比用于形成漏极偏移区域的P型杂质的浓度峰值更深的位置。
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公开(公告)号：US07485972B2
公开(公告)日：2009-02-03
申请号：US11356144
申请日：2006-02-17
IPC分类号： H01L23/12
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05552 , H01L2224/05624 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/05042 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate even when a breakdown occurs during wire bonding.
摘要翻译： 提供了一种半导体器件，其包括形成在第一导电类型的半导体衬底上的导电焊盘，其经由绝缘膜和在接合焊盘下形成在半导体衬底的表面上的第二导电类型的扩散层。 即使在引线接合期间发生击穿，特性也不会劣化。
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公开(公告)号：US20060202240A1
公开(公告)日：2006-09-14
申请号：US11356144
申请日：2006-02-17
IPC分类号： H01L29/76
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05552 , H01L2224/05624 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/05042 , H01L2924/12036 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Provided is a semiconductor device which includes a conductive bonding pad formed on a semiconductor substrate of the first conduction type via an insulating film and a diffusion layer of the second conduction type formed on a surface of the semiconductor substrate under the bonding pad. Characteristics do not deteriorate even when a breakdown occurs during wire bonding.
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公开(公告)号：US07157772B2
公开(公告)日：2007-01-02
申请号：US11167429
申请日：2005-06-28
申请人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/7824 , H01L29/402 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/66681
摘要： A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.
摘要翻译： 栅电极的一端延伸到LOCOS氧化膜的一部分上，并且源极电极的一端延伸得比LOCOS氧化膜的一部分上的栅电极的端部更远。 形成覆盖栅电极和LOCOS氧化物膜的绝缘膜，使得位于栅电极的端部上的端部区域上的绝缘膜的厚度设置成延伸到LOCOS氧化物膜的一部分上 从支撑基板的主表面观察，小于在漏极区域之上的源电极的端部下方的绝缘膜的厚度，并且小于栅电极的端部上的绝缘膜的厚度 在身体区域之上。
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公开(公告)号：US20060017105A1
公开(公告)日：2006-01-26
申请号：US11167429
申请日：2005-06-28
申请人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
发明人： Hiroyoshi Ogura , Hisao Ichijo , Yoshinobu Sato , Teruhisa Ikuta
CPC分类号： H01L29/7824 , H01L29/402 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/66681
摘要： A gate electrode has an end extended over a part of a LOCOS oxide film, and a source electrode has an end extended further than the end of the gate electrode over a part of the LOCOS oxide film. An insulating film covering the gate electrode and the LOCOS oxide film is formed such that the thickness of the insulating film at an end-portion region, which is on an end portion of the gate electrode provided to extend over a part of the LOCOS oxide film, as viewed from a main surface of a supporting substrate, is smaller than the thickness of the insulating film below an end portion of the source electrode above the drain region and smaller than the thickness of the insulating film on an end portion of the gate electrode above a body region.
摘要翻译： 栅电极的一端延伸到LOCOS氧化膜的一部分上，并且源极电极的一端延伸得比LOCOS氧化膜的一部分上的栅电极的端部更远。 形成覆盖栅电极和LOCOS氧化物膜的绝缘膜，使得位于栅电极的端部上的端部区域上的绝缘膜的厚度设置成延伸到LOCOS氧化物膜的一部分上 从支撑基板的主表面观察，小于在漏极区域之上的源电极的端部下方的绝缘膜的厚度，并且小于栅电极的端部上的绝缘膜的厚度 在身体区域之上。
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