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63 条记录 (耗时 0.027 秒)

    Bipolar transistor and method for fabricating the same
    3.
    发明授权
    Bipolar transistor and method for fabricating the same 有权
    双极晶体管及其制造方法

    公开(公告)号：US07091099B2

    公开(公告)日：2006-08-15

    申请号：US10807307

    申请日：2004-03-24

    申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

    发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

    摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

    Bipolar transistor and method for fabricating the same
    5.
    发明授权
    Bipolar transistor and method for fabricating the same 有权
    双极晶体管及其制造方法

    公开(公告)号：US07465969B2

    公开(公告)日：2008-12-16

    申请号：US11450474

    申请日：2006-06-12

    申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

    发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/66242 ,  H01L29/7378

    摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

    摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

    Semiconductor device and method for fabricating the same
    6.
    发明授权
    Semiconductor device and method for fabricating the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06399993B1

    公开(公告)日：2002-06-04

    申请号：US09786551

    申请日：2001-03-07

    申请人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

    发明人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

    IPC分类号： H01L2972

    CPC分类号： H01L21/76237 ,  H01L21/8249

    摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

    摘要翻译： 在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。 在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。 基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。 用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。 由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

    Method for fabricating semiconductor device
    9.
    发明授权
    Method for fabricating semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06620665B1

    公开(公告)日：2003-09-16

    申请号：US09787108

    申请日：2001-03-14

    申请人： Gaku Sugahara ,  Tohru Saitoh ,  Minoru Kubo ,  Teruhito Ohnishi

    发明人： Gaku Sugahara ,  Tohru Saitoh ,  Minoru Kubo ,  Teruhito Ohnishi

    IPC分类号： H01L21338

    CPC分类号： H01L29/66916 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/66242

    摘要： A process control is performed for fabricating both a wafer for a device including a Ge-containing semiconductor film and a wafer for a device, for example, including no Ge-containing semiconductor film on a common fabrication line. When the wafer including the Ge-containing semiconductor film is to be subjected to high-temperature treatment at 700° C. or more in the state of the Ge-containing semiconductor film being substantially exposed, the Ge-containing semiconductor film is covered with a cap layer made of Si or the like before the high-temperature treatment. The cap layer may be formed on the common fabrication line. However, if the formation of the cap layer itself involves high temperature of 700° C. or more, it is performed on a fabrication line separate from the common fabrication line. Alternatively, the cap layer may be formed on a fabrication line separate from the common fabrication line and the high-temperature treatment at 700° C. or more may also be performed on a separate fabrication line. Otherwise, it suffices to only perform the high-temperature treatment at 700° C. or more on a separate line.

    摘要翻译： 执行用于制造包括含Ge半导体膜和用于器件的晶片的器件的晶片的工艺控制，例如在公共制造线上不包含含Ge半导体膜。 在含有Ge的半导体膜的晶片在Ge基半导体膜的状态基本上露出的状态下，在700℃以上进行高温处理时，含有Ge的半导体膜被覆盖 在高温处理之前由Si等制成的盖层。 盖层可以形成在公共制造线上。 然而，如果盖层本身的形成涉及700℃以上的高温，则在与公共制造线分开的制造线上进行。 或者，盖层可以形成在与公共制造线分开的制造线上，并且在700℃以上的高温处理也可以在单独的制造线上进行。 否则，仅在单独的线路上进行700℃以上的高温处理即可。

    Method of producing semiconductor crystal
    10.
    发明授权
    Method of producing semiconductor crystal 失效
    半导体晶体的制造方法

    公开(公告)号：US06987072B2

    公开(公告)日：2006-01-17

    申请号：US11009020

    申请日：2004-12-13

    申请人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

    发明人： Yoshihiko Kanzawa ,  Teruhito Ohnishi ,  Ken Idota ,  Tohru Saitoh ,  Akira Asai

    IPC分类号： H01L21/31

    CPC分类号： H01L21/324 ,  C30B23/02 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/322 ,  Y10S438/933

    摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

    摘要翻译： 一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加 能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。 该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。