公开(公告)号：US07091099B2

公开(公告)日：2006-08-15

申请号：US10807307

申请日：2004-03-24

申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

公开(公告)号：US07465969B2

公开(公告)日：2008-12-16

申请号：US11450474

申请日：2006-06-12

申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

摘要翻译： 双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极 ，和发射极层。 在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。 发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

公开(公告)号：US20060226446A1

公开(公告)日：2006-10-12

申请号：US11450474

申请日：2006-06-12

申请人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

发明人： Teruhito Ohnishi ,  Koichiro Yuki ,  Tsuneichiro Sano ,  Tohru Saitoh ,  Ken Idota ,  Takahiro Kawashima ,  Shigeki Sawada

IPC分类号： H01L31/00

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.

公开(公告)号：US07719031B2

公开(公告)日：2010-05-18

申请号：US10564085

申请日：2004-07-06

申请人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

发明人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

IPC分类号： H01L29/74

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

摘要翻译： 双极晶体管120包括衬底1，本征基极区域11和非本征基极区域12.本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和组成比分级基底 层111，其形成在硅缓冲层上并且包含硅并且至少为锗，并且其中锗与硅的组成比在组成比梯度基底层111的厚度方向上变化。外部基极区12包括 外部基底形成层113由硅构成，其形成在衬底上并与硅缓冲层相邻。 外部基底形成层113的厚度不小于40nm。

公开(公告)号：US20070085167A1

公开(公告)日：2007-04-19

申请号：US10564085

申请日：2004-07-06

申请人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

发明人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

摘要翻译： 双极晶体管120包括衬底1，本征基极区域11和外部基极区域12。 本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和形成在硅缓冲层上并包含硅和至少锗的组成比梯度的基底层111，其中组成 锗与硅的比例在组成比梯度的基底层111的厚度方向上变化。 外部基极区域12包括由硅构成的非本征基底形成层113，其形成在衬底上并与硅缓冲层相邻。 外部基底形成层113的厚度不小于40nm。

公开(公告)号：US08106382B2

公开(公告)日：2012-01-31

申请号：US12305824

申请日：2007-06-18

申请人： Tohru Saitoh ,  Takahiro Kawashima

发明人： Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L29/66

CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/41733 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A source electrode 105 which is connected to a portion of at least one semiconductor nanostructure 103 among a plurality of semiconductor nanostructures, a drain electrode 106 connected to another portion of the semiconductor nanostructure 103, and a gate electrode 102 capable of controlling electrical conduction of the semiconductor nanostructure 103 are included. The semiconductor nanostructures 103 include a low concentration region 108 having a relatively low doping concentration and a pair of high concentration regions 107 having a higher doping concentration than that of the low concentration region 108 and being connected to both ends of the low concentration region 108. The doping concentration of the high concentration regions 107 is 1×1019 cm−3 or more; the length of the low concentration region 108 is shorter than a length of the gate electrode 102 along a direction from the source electrode 105 to the drain electrode 106; and the length of the gate electrode 102 is shorter than the interspace between the source electrode 105 and the drain electrode 106.

摘要翻译： 连接到多个半导体纳米结构中的至少一个半导体纳米结构103的一部分的源电极105，连接到半导体纳米结构103的另一部分的漏电极106和能够控制半导体纳米结构103的导电的栅电极102 包括半导体纳米结构103。 半导体纳米结构103包括具有相对低的掺杂浓度的低浓度区域108和具有比低浓度区域108的掺杂浓度更高的掺杂浓度的一对高浓度区域107并且连接到低浓度区域108的两端。 高浓度区域107的掺杂浓度为1×1019cm-3以上; 低浓度区域108的长度比沿源极电极105至漏电极106的方向的栅电极102的长度短; 并且栅电极102的长度比源电极105和漏电极106之间的间隙短。

公开(公告)号：US20100224915A1

公开(公告)日：2010-09-09

申请号：US12159352

申请日：2007-01-12

申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Tohru Nakagawa ,  Hideo Torii

发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Tohru Nakagawa ,  Hideo Torii

IPC分类号： H01L29/78 ,  H01L21/20 ,  H01L21/336

CPC分类号： H01L27/1266 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1285 ,  H01L27/1292

摘要： According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).

摘要翻译： 根据本发明的用于制造半导体片的方法，首先通过在衬底（10）上层叠牺牲层（11）和半导体层（12）来形成至少两个半导体层（12） 10），并重复该堆叠。 接下来，通过蚀刻部分牺牲层（11）和部分半导体层（12）将半导体层（12）分割成多个。 然后，通过去除牺牲层（11）将片与衬底分离。

公开(公告)号：US20060208300A1

公开(公告)日：2006-09-21

申请号：US10549291

申请日：2004-03-19

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US08242025B2

公开(公告)日：2012-08-14

申请号：US12159352

申请日：2007-01-12

申请人： Takahiro Kawashima ,  Tohru Saitoh ,  Tohru Nakagawa ,  Hideo Torii

发明人： Takahiro Kawashima ,  Tohru Saitoh ,  Tohru Nakagawa ,  Hideo Torii

IPC分类号： H01L21/301

CPC分类号： H01L27/1266 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1285 ,  H01L27/1292

摘要： According to a method of the present invention for manufacturing a semiconductor piece, at least two semiconductor layers (12) are first formed on a substrate (10) by stacking a sacrificial layer (11) and the semiconductor layer (12) on the substrate (10) in this order and repeating this stacking. Next, the semiconductor layers (12) are divided into pieces by etching part of the sacrificial layers (11) and part of the semiconductor layers (12). Then, the pieces are separated from the substrate by removing the sacrificial layers (11).

摘要翻译： 根据本发明的用于制造半导体片的方法，首先通过在衬底（10）上层叠牺牲层（11）和半导体层（12）来形成至少两个半导体层（12） 10），并重复该堆叠。 接下来，通过蚀刻部分牺牲层（11）和部分半导体层（12）将半导体层（12）分割成多个。 然后，通过去除牺牲层（11）将片与衬底分离。

公开(公告)号：US20100133509A1

公开(公告)日：2010-06-03

申请号：US12451898

申请日：2008-06-04

申请人： Takahiro Kawashima ,  Tohru Saitoh

发明人： Takahiro Kawashima ,  Tohru Saitoh

IPC分类号： H01L29/775 ,  H01L21/04

CPC分类号： H01L21/02653 ,  B82Y10/00 ,  B82Y30/00 ,  C30B11/12 ,  C30B25/00 ,  C30B29/06 ,  C30B29/40 ,  C30B29/60 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02603 ,  H01L21/02656 ,  H01L27/3262 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/775 ,  H01L33/18 ,  Y10S438/962

摘要： A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

摘要翻译： 提供一种制造具有第一和第二区域的半导体纳米线的方法。 将催化剂颗粒放在基材上。 引入第一源气体，从而通过气 - 液 - 固相生长从催化剂颗粒生长第一区域。 在第一区域的侧壁上形成保护涂层，并且引入第二源气体以通过液相 - 固相生长从第一区域延伸出第二区域。