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    Systems and methods for producing flat surfaces in interconnect structures
    5.
    发明授权
    Systems and methods for producing flat surfaces in interconnect structures 有权

    公开(公告)号：US10804151B2

    公开(公告)日：2020-10-13

    申请号：US15834354

    申请日：2017-12-07

    申请人： TESSERA, INC.

    发明人： Cyprian Emeka Uzoh ,  Vage Oganesian ,  Ilyas Mohammed

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/321 ,  H01L23/48 ,  H01L23/532

    摘要： In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.

    HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS
    7.
    发明申请
    HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS 有权
    高密度三维集成电容器

    公开(公告)号：US20160079189A1

    公开(公告)日：2016-03-17

    申请号：US14934544

    申请日：2015-11-06

    申请人： Tessera, Inc.

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Emeka Uzoh ,  Piyush Savalia ,  Vage Oganesian

    IPC分类号： H01L23/64 ,  H01L49/02

    CPC分类号： H01L23/642 ,  H01G4/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0657 ,  H01L25/16 ,  H01L28/40 ,  H01L28/91 ,  H01L28/92 ,  H01L2223/6622 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.

    摘要翻译： 电容器可以包括具有第一表面的基板，远离第一表面的第二表面，以及在第一和第二表面之间延伸的通孔，第一和第二金属元件以及将第一和第二表面分离和绝缘的电容器介电层 至少在通孔内的金属元​​件彼此之间。 第一金属元件可以在第一表面暴露并且可以延伸到通孔中。 第二金属元件可以在第二表面处露出并且可以延伸到通孔中。 第一和第二金属元件可以电连接到第一和第二电位。 电容器介电层可以具有起伏的形状。

    VIAS IN POROUS SUBSTRATES
    8.
    发明申请
    VIAS IN POROUS SUBSTRATES 有权
    多孔基材中的VIAS

    公开(公告)号：US20150140807A1

    公开(公告)日：2015-05-21

    申请号：US14610300

    申请日：2015-01-30

    申请人： Tessera, Inc.

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Emeka Uzoh ,  Piyush Savalia

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/486 ,  H01L21/76837 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

    摘要翻译： 微电子单元可以包括其中具有前表面和后表面的基板和其中的有源半导体器件，所述基板具有布置成在后表面的区域上的对称或不对称分布的多个开口，连接到第一和第二导电通孔的第一和第二导电通孔 在前表面暴露的焊盘，在相应的一个开口内延伸的多个第一和第二导电互连，以及暴露以与外部元件互连的第一和第二导电触点。 多个第一导电互连可以通过所述多个开口中的至少一个与所述多个第二导电互连部分开，所述至少一个开口至少部分地填充有绝缘材料。 开口的分布可以包括在第一方向上间隔开的至少m个开口和在横向于第一方向的第二方向上间隔开的n个开口。

    Low stress vias
    9.
    发明授权
    Low stress vias 有权

    公开(公告)号：US10283449B2

    公开(公告)日：2019-05-07

    申请号：US15597699

    申请日：2017-05-17

    申请人： Tessera, Inc.

    发明人： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Emeka Uzoh

    IPC分类号： H01L23/522 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768

    摘要： A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.