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47 条记录 (耗时 0.037 秒)

    Electronic device
    3.
    发明授权
    Electronic device 失效
    电子设备

    公开(公告)号：US5670790A

    公开(公告)日：1997-09-23

    申请号：US718186

    申请日：1996-09-19

    申请人： Riichi Katoh ,  Tetsufumi Tanamoto ,  Shigeki Takahashi

    发明人： Riichi Katoh ,  Tetsufumi Tanamoto ,  Shigeki Takahashi

    IPC分类号： H01L21/8247 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L29/88 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

    CPC分类号： H01L29/7883 ,  H01L29/8616 ,  H01L29/88

    摘要： An electronic device which includes, a couple of first conduction regions which are capable of confining carriers, a second conduction region having a higher energy level than those of the first conduction regions, and a first electrode for impressing a voltage on the first conduction regions, wherein when a voltage is impressed via the first electrode between the couple of first conduction regions, carriers are caused to move due to a tunneling effect from one of the first conduction regions via the second conduction region to the other of the first conduction regions, and when the voltage impressed between the couple of first conduction regions is removed, carriers are confined mainly in the one of the first conduction regions.

    摘要翻译： 一种电子设备，包括能够限制载流子的一对第一导电区域，具有比第一导电区域更高的能级的第二导电区域和用于在第一导电区域上施加电压的第一电极， 其中当通过所述第一导电区域之间的所述第一电极施加电压时，由于所述第一导电区域中的一个通过所述第二导电区域到所述第一导电区域中的另一个导致的载流子由于隧道效应而移动，以及 当去除在一对第一导电区域之间施加的电压时，载流子主要被限制在第一导电区域中的一个中。

    Single-electron semiconductor device
    5.
    发明授权
    Single-electron semiconductor device 失效
    单电子半导体器件

    公开(公告)号：US5844279A

    公开(公告)日：1998-12-01

    申请号：US713365

    申请日：1996-09-13

    申请人： Tetsufumi Tanamoto ,  Riichi Katoh

    发明人： Tetsufumi Tanamoto ,  Riichi Katoh

    IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L27/01

    CPC分类号： B82Y10/00 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7613 ,  Y10S977/937

    摘要： A semiconductor device which includes, a substrate, an insulating layer formed on the substrate, a silicon layer having an exposed surface constituted by a Si (100) face, the silicon layer being provided with a tapered recess having a bottom at which a part of the silicon layer is remained without exposing the insulating layer, a first conductive region constituted by the silicon layer remaining at the bottom of the tapered recess, a second and a third conductive regions formed on both sides of the tapered recess respectively, a first insulating film formed on an inner surface of the tapered recess, and an electrode formed in the tapered recess. A flow of electron resulting from the tunneling effect from the second conductive region via the first insulating film to the third conductive region is controlled by controlling a voltage to be impressed onto the electrode.

    摘要翻译： 一种半导体器件，包括：衬底，形成在所述衬底上的绝缘层，具有由Si（100）面构成的暴露表面的硅层，所述硅层设置有具有底部的锥形凹部， 在不暴露绝缘层的情况下保留硅层，由保留在锥形凹部的底部的硅层构成的第一导电区域，分别形成在锥形凹槽两侧的第二和第三导电区域，第一绝缘膜 形成在锥形凹部的内表面上，以及形成在锥形凹部中的电极。 通过控制施加到电极上的电压来控制从第二导电区域经由第一绝缘膜到第三导电区域的隧穿效应所产生的电子流。

    Programmable logic circuit
    6.
    发明授权
    Programmable logic circuit 有权
    可编程逻辑电路

    公开(公告)号：US08294489B2

    公开(公告)日：2012-10-23

    申请号：US12404606

    申请日：2009-03-16

    申请人： Tetsufumi Tanamoto ,  Hideyuki Sugiyama ,  Kazutaka Ikegami ,  Yoshiaki Saito

    发明人： Tetsufumi Tanamoto ,  Hideyuki Sugiyama ,  Kazutaka Ikegami ,  Yoshiaki Saito

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1776 ,  G11C13/0002 ,  H03K19/17764 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/18

    摘要： A programmable logic circuit includes: an input circuit configured to receive a plurality of input signals; and a programmable cell array including a plurality of unit programmable cells arranged in a matrix form, each of the unit programmable cells including a first memory circuit of resistance change type including a first transistor and a second memory circuit of resistance change type including a second transistor, the first and second memory circuits connected in parallel, each gate of the first transistors on same row respectively receiving one input signal, each gate of the second transistors on same row receiving an inverted signal of the one input signal, output terminals of the first and second memory circuits on same column being connected to a common output line.

    摘要翻译： 可编程逻辑电路包括：输入电路，被配置为接收多个输入信号; 以及包括以矩阵形式布置的多个单元可编程单元的可编程单元阵列，每个单元可编程单元包括电阻改变型的第一存储器电路，包括第一晶体管和包括第二晶体管的电阻变化型的第二存储器电路 并联连接的第一和第二存储器电路，同一行上的第一晶体管的每个栅极分别接收一个输入信号，同一行上的第二晶体管的每个栅极接收一个输入信号的反相信号，第一个输出端的输出端 并且同一列上的第二存储器电路连接到公共输出线。

    Nonvolatile memory circuit using spin MOS transistors
    7.
    发明授权
    Nonvolatile memory circuit using spin MOS transistors 有权
    使用自旋MOS晶体管的非易失性存储电路

    公开(公告)号：US08154916B2

    公开(公告)日：2012-04-10

    申请号：US12889881

    申请日：2010-09-24

    申请人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki Sugiyama ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： G11C11/14

    CPC分类号： G11C14/0081

    摘要： Certain embodiments provide a nonvolatile memory circuit in which a first p-channel MOS transistor and a first n-channel spin MOS transistor are connected in series, a second p-channel MOS transistor and a second n-channel spin MOS transistor are connected in series, gates of the first p-channel MOS transistor and the first n-channel spin MOS transistor are connected, gates of the second p-channel MOS transistor and the second n-channel spin MOS transistor are connected, a first n-channel transistor includes a drain connected to a drain of the first p-channel transistor and the gate of the second p-channel transistor, a second n-channel transistor includes a drain connected to a drain of the second p-channel transistor and the gate of the first p-channel transistor, and gates of the first and second n-channel transistors are connected.

    摘要翻译： 某些实施例提供了其中第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管串联连接的非易失性存储器电路，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管串联连接 第一p沟道MOS晶体管和第一n沟道自旋MOS晶体管的栅极连接，第二p沟道MOS晶体管和第二n沟道自旋MOS晶体管的栅极连接，第一n沟道晶体管包括 连接到第一p沟道晶体管的漏极和第二p沟道晶体管的栅极的漏极，第二n沟道晶体管包括连接到第二p沟道晶体管的漏极和第一p沟道晶体管的栅极的漏极 p沟道晶体管，第一和第二n沟道晶体管的栅极连接。

    LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY
    8.
    发明申请
    LOOK-UP TABLE CIRCUITS AND FIELD PROGRAMMABLE GATE ARRAY 有权
    查看表电路和现场可编程门阵列

    公开(公告)号：US20120074984A1

    公开(公告)日：2012-03-29

    申请号：US13238020

    申请日：2011-09-21

    申请人： Hideyuki SUGIYAMA ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    发明人： Hideyuki SUGIYAMA ,  Tetsufumi Tanamoto ,  Takao Marukame ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

    IPC分类号： H03K19/177 ,  H03K5/00

    CPC分类号： H03K19/177

    摘要： A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.

    摘要翻译： 根据实施例的查找表电路包括：可变电阻电路，包括可变电阻器件，并且基于输入信号从可变电阻器件中选择可变电阻器件; 参考电路，其具有可变电阻电路的最大电阻值和最小电阻值之间的电阻值; 第一n沟道MOSFET，其包括连接到可变电阻电路的端子的源极和连接到漏极的栅极; 第二n沟道MOSFET，其包括连接到参考电路的端子的源极和连接到第一n沟道MOSFET的栅极的栅极; 用于向可变电阻电路提供电流的第一电流供应电路; 第二电流供应电路，用于向参考电路提供电流; 以及比较器，用于比较第一输入端和第二输入端的电压。

    RANDOM NUMBER GENERATION DEVICE
    10.
    发明申请
    RANDOM NUMBER GENERATION DEVICE 审中-公开
    随机数生成装置

    公开(公告)号：US20090309646A1

    公开(公告)日：2009-12-17

    申请号：US12391640

    申请日：2009-02-24

    申请人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

    发明人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

    IPC分类号： G06G7/12 ,  H01L27/088

    CPC分类号： H01L29/1054 ,  G06F7/588 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/7843 ,  H03K3/84

    摘要： A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.

    摘要翻译： 随机数生成装置包括：第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一绝缘膜; 以及设置在第一绝缘膜上的第一栅电极。 第一绝缘膜具有陷阱捕获和释放电荷，并且在栅极长度方向上向第一沟道区和第一绝缘膜中的至少一个施加拉伸或压缩应力。