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公开(公告)号：US5575851A
公开(公告)日：1996-11-19
申请号：US141638
申请日：1993-10-27
CPC分类号： B29C47/16 , B05C5/0266 , B29C47/0019 , B29C47/003 , B29C47/0033
摘要： Disclosed herein is a die coater comprising a die composed of upper and lower mold-pieces which form a manifold and a slit extending from the manifold, an inner deckle shaft disposed in the manifold, a deckle disposed in the slit in a fluid-tight state, and a deckle guide; the inner deckle shaft having a fluid-tight portion near an end thereof and capable of moving with its fluid-tight state kept, the deckle and the deckle guide being secured to the inner deckle shaft, and the deckle being connected with the fluid-tight portion of the inner deckle shaft.
摘要翻译： 本文公开了一种模具涂布机，其包括由上模具和下模具构成的模具，所述模具形成歧管和从歧管延伸的狭缝，设置在歧管中的内层板轴，以流体密封状态设置在狭缝中的板 ，和一个甲板导轨; 内层板轴在其端部附近具有流体密封部分，并且能够保持其流体密封状态移动，甲板和甲板导向件固定到内板轴上，并且该盖板与流体密封连接 内板轴的一部分。
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公开(公告)号：US5399196A
公开(公告)日：1995-03-21
申请号：US99129
申请日：1993-07-29
CPC分类号： B05C5/0254 , B05C11/1036 , B05B12/14
摘要： A die coater comprising a die composed of upper and lower mold-pieces which form a manifold and a slit extending from the manifold, a first paint supply pipe communicating with one end portion of the manifold, a second paint supply pipe communicating with another end portion of the manifold and a flow channel closing member disposed in the manifold in a fluid sealing state, the member being movable along the manifold.
摘要翻译： 一种模涂机，包括由上模和下模组成的模具，其形成歧管和从歧管延伸的狭缝，与歧管的一个端部连通的第一涂料供应管，与另一端部连通的第二涂料供应管 并且流体通道关闭构件以流体密封状态设置在歧管中，该构件可沿歧管移动。
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公开(公告)号：US07149267B2
公开(公告)日：2006-12-12
申请号：US10995124
申请日：2004-11-24
申请人： Yutaka Terada , Takefumi Yoshikawa
发明人： Yutaka Terada , Takefumi Yoshikawa
IPC分类号： H04L7/00
CPC分类号： G11C7/1093 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/22
摘要： An input circuit includes: a comparator; first and second delay circuits; a selector; an input buffer; and a holding circuit. The comparator compares the leading and/or trailing edges of a data signal, supplied from the input buffer, to an edge of a clock signal on which the data signal is intended to be latched. Based on the results of the comparison, the first and second delay circuits delay the clock signal for respectively predetermined amounts of time. If the data signal is logically high, then the selector selects a delayed clock signal supplied from the first delay circuit. Alternatively, if the data signal is logically low, then the selector selects another delayed clock signal supplied from the second delay circuit. Then, the delayed clock signal, selected by the selector, is latched in the holding circuit. The input circuit with such a configuration prevents skewing from being caused by a difference in length between the transition interval of the data signal from H into L level and that of the data signal from L into H level. As a result, data can be transferred at a much higher speed even if the clock frequency is very high.
摘要翻译： 输入电路包括：比较器; 第一和第二延迟电路; 选择器 一个输入缓冲区; 和保持电路。 比较器将从输入缓冲器提供的数据信号的前沿和/或后沿比较到要锁存数据信号的时钟信号的边沿。 基于比较结果，第一和第二延迟电路分别延迟时钟信号预定的时间量。 如果数据信号逻辑高，则选择器选择从第一延迟电路提供的延迟时钟信号。 或者，如果数据信号在逻辑上低，则选择器选择从第二延迟电路提供的另一延迟时钟信号。 然后，由选择器选择的延迟时钟信号被锁存在保持电路中。 具有这种配置的输入电路防止由数据信号从H变为L电平的过渡间隔和从L变为H电平的数据信号之间的长度差引起的偏移。 因此，即使时钟频率非常高，也可以以更高的速度传输数据。
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4.发明授权Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit 失效用于PLL，锁相环和半导体集成电路的低通滤波器公开(公告)号：US07030688B2
公开(公告)日：2006-04-18
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03K5/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。
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公开(公告)号：US20050237822A1
公开(公告)日：2005-10-27
申请号：US11113172
申请日：2005-04-25
IPC分类号： G11C5/00
CPC分类号： G06F1/12 , G06F13/4243 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4093 , H04L7/0012
摘要： A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.
摘要翻译： 即使当用于输出数据的时钟信号的速度增加时，再同步电路也具有足够的迁移余量，从而可以提高数据传输速度。 在再同步电路中，确定电路保持根据确定信号和参考时钟信号之间的相位差确定的信号（确定结果）。 在同步电路块中，接收到的数据信号与选通信号同步地保持。 然后，接收到的数据信号与具有与参考时钟信号的频率相同的频率的时钟信号同步地保持，并且具有根据确定结果确定的相位和从再同步电路输出的相位。
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公开(公告)号：US6151268A
公开(公告)日：2000-11-21
申请号：US233317
申请日：1999-01-19
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
CPC分类号： G06F12/0879 , G06F12/08 , G11C11/005 , G11C7/1072
摘要： A semiconductor memory includes a plurality of memory cells; and an access section for accessing a memory cell, among the plurality of memory cells, corresponding to a row address and a column address. The plurality of memory cells include at least one first memory cell accessible at a first access speed and at least one second memory cell accessible at a second access speed which is higher than the first access speed. The at least one second memory cell is assigned to at least one specified column address.
摘要翻译： 半导体存储器包括多个存储单元; 以及访问部分，用于访问所述多个存储器单元中对应于行地址和列地址的存储器单元。 多个存储器单元包括以第一访问速度可访问的至少一个第一存储器单元和以比第一访问速度高的第二访问速度可访问的至少一个第二存储单元。 至少一个第二存储器单元被分配给至少一个指定的列地址。
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公开(公告)号：US20100283525A1
公开(公告)日：2010-11-11
申请号：US12811489
申请日：2008-10-28
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： H03K5/13
CPC分类号： H03K5/156 , H03K3/84 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814 , H03L7/0998 , H04B15/02 , H04B2215/067
摘要： A phase control device that adjusts a phase of a clock receives a first clock, a second clock and a control code. The phase control device includes phase adjusters (PI-11, PI-12), PI-2 and PI-3 that output a clock of a phase corresponding to the control code. These phase adjusters are connected in a three-stages cascade. The control codes of these phase adjusters (PI-11, PI-12), PI-2 and PI-3 are varied in association with each other. Therefore, as compared with a case where a phase of a clock is adjusted by a phase adjuster alone, if a resolution (adjustment granularity) of each phase adjuster is defined as N, it is possible to reduce the adjustment granularity of a phase as small as N to the power of the number of the stages. Therefore, when the phase control device is used for a SSC, the peak power reduction value is improved.
摘要翻译： 调整时钟相位的相位控制装置接收第一时钟，第二时钟和控制代码。 相位控制装置包括相位调节器（PI-11，PI-12），PI-2和PI-3，其输出与控制代码对应的相位的时钟。 这些相位调节器以三级级联连接。 这些相位调节器（PI-11，PI-12），PI-2和PI-3的控制代码彼此相关地变化。 因此，与通过相位调整器单独调整时钟的相位的情况相比，如果将各相位调整器的分辨率（调整粒度）定义为N，则可以将相位的调整粒度降低为小 作为N次数的阶段的力量。 因此，当相位控制装置用于SSC时，峰值功率降低值得以改善。
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公开(公告)号：US07233215B2
公开(公告)日：2007-06-19
申请号：US11000224
申请日：2004-12-01
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
IPC分类号： H03C3/00
CPC分类号： H04B15/02 , H03K7/06 , H04B2215/067
摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.
摘要翻译： 频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。
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公开(公告)号：US07176708B2
公开(公告)日：2007-02-13
申请号：US10716615
申请日：2003-11-20
申请人： Tsuyoshi Ebuchi , Toru Iwata , Takefumi Yoshikawa
发明人： Tsuyoshi Ebuchi , Toru Iwata , Takefumi Yoshikawa
IPC分类号： H03K19/007
CPC分类号： H04L25/493
摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。
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公开(公告)号：US06392462B1
公开(公告)日：2002-05-21
申请号：US09824220
申请日：2001-04-03
IPC分类号： H03K300
摘要： A multiphase clock generator includes oscillator, selector circuit and frequency divider circuit. The oscillator generates a first multiphase clock having a first phase difference. The selector circuit receives the first multiphase clock from the oscillator and outputs a second multiphase clock including a plurality of clock signals. In the second multiphase clock, the phase of each clock signal is shifted from that of the previous one by a second phase difference. The second phase difference is n times as long as the first phase difference, where n is a predetermined positive integer. And the frequency divider circuit receives the second multiphase clock from the selector circuit, divides the frequency of the second multiphase clock by a predetermined number and then outputs a group of clock signals with the divided frequency as a third multiphase clock.
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