公开(公告)号：US08908345B2

公开(公告)日：2014-12-09

申请号：US13332861

申请日：2011-12-21

申请人： Futoshi Furuta ,  Kenichi Osada

发明人： Futoshi Furuta ,  Kenichi Osada

IPC分类号： H01L27/02 ,  H02H9/04 ,  H01L25/065 ,  H01L23/62 ,  H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/62 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H02H9/046

摘要： In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.

摘要翻译： 在堆叠式芯片系统中，连接到用于IO的TSV焊盘和开关电路的IO电路构成每个芯片中的IO通道，与最大预定堆栈数量一样多的IO通道耦合在一起并连接以构成IO组 ，并且芯片具有一个或多个这样的IO组。 用于IO的每个TSV焊盘与通孔连接到另一层的芯片中相同位置处的IO端子。 在插入器上，如果堆栈的实际数量小于堆栈的最大预定数量，则插入器上相邻IO组中IO的连接焊盘将通过导线连接。

公开(公告)号：US08233105B2

公开(公告)日：2012-07-31

申请号：US12417898

申请日：2009-04-03

申请人： Hiroshi Kageyama ,  Futoshi Furuta ,  Ken Takei

发明人： Hiroshi Kageyama ,  Futoshi Furuta ,  Ken Takei

IPC分类号： G02F1/1343 ,  G06F3/038

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/13452

摘要： In order to restrain increase in frame area caused along with a larger number of channels to a minimum, there is provided an image display device that adopts a communication method in which a signal is transmitted/received with the use of electrostatic capacitance coupling. A first board includes: a tabular first power supply line, a tabular second power supply line, a semiconductor element, and a tabular first electrode group. A second board includes: a tabular second electrode group and a tabular common electrode. In a state where the first board and the second board are laid on each other, the first electrode group overlaps the second electrode group while one of the first power supply line and the second power supply line overlaps the common electrode.

摘要翻译： 为了将更多数量的通道引起的帧区域的增加抑制到最小，提供了一种图像显示装置，其采用使用静电电容耦合来发送/接收信号的通信方法。 第一板包括：片状第一电源线，平板状第二电源线，半导体元件和平板状第一电极组。 第二板包括：片状第二电极组和平板状公共电极。 在第一板和第二板彼此铺设的状态下，第一电极组与第二电极组重叠，而第一电源线和第二电源线中的一个与公共电极重叠。

公开(公告)号：US08184252B2

公开(公告)日：2012-05-22

申请号：US12509602

申请日：2009-07-27

申请人： Futoshi Furuta ,  Hiroshi Kageyama ,  Ken Takei

发明人： Futoshi Furuta ,  Hiroshi Kageyama ,  Ken Takei

IPC分类号： G02F1/1343 ,  G02F1/1345

CPC分类号： G02F1/1368 ,  G02F2001/134318 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0426

摘要： An image display device includes a display panel having plural pixels and a second board having a transmitting electrode, the display panel having a first substrate that is disposed so as to overlap the second board, each pixel having a pixel electrode and a counter electrode, and the counter electrode being formed in a planar shape and being commonly provided to the pixel electrodes of each pixel; the counter electrode being divided into a portion A corresponding to the transmitting electrode of the second board and a portion B other than it, and the portions A and B of the counter electrode being connected to a common voltage through resistors. The portion A of the counter electrode constitutes the receiving electrode, and the portion A of the counter electrode acting as the receiving electrode is connected to a receiving circuit in the display panel through a decoupling capacitor.

摘要翻译： 图像显示装置包括具有多个像素的显示面板和具有发送电极的第二基板，所述显示面板具有与所述第二基板重叠地配置的第一基板，每个像素具有像素电极和对置电极， 该对电极形成为平面形状，并且共同地设置在每个像素的像素电极上; 对置电极被分成对应于第二板的发送电极的部分A和除了它之外的部分B，并且对电极的部分A和B通过电阻器连接到公共电压。 对置电极的部分A构成接收电极，并且用作接收电极的对置电极的部分A通过去耦电容器连接到显示面板中的接收电路。

公开(公告)号：US08148814B2

公开(公告)日：2012-04-03

申请号：US12699006

申请日：2010-02-02

申请人： Futoshi Furuta ,  Kenichi Osada ,  Makoto Saen

发明人： Futoshi Furuta ,  Kenichi Osada ,  Makoto Saen

IPC分类号： H01L23/34

CPC分类号： H01L25/18 ,  G11C5/04 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

摘要翻译： 在以N级堆叠的半导体芯片的通孔通路中，在各半导体芯片中设置有中继电路。 例如，从半导体芯片的输出缓冲电路发送的信号经由各半导体芯片的中继电路发送到半导体芯片的输入缓冲电路。 各个中继器电路可以隔离输入侧和输出侧的阻抗，因此可以减少伴随着各个半导体芯片的通孔通路寄生的寄生电容的波形质量的劣化，并且可以降低高速信号 可以传输。

公开(公告)号：US20100200998A1

公开(公告)日：2010-08-12

申请号：US12699006

申请日：2010-02-02

申请人： Futoshi FURUTA ,  Kenichi Osada ,  Makoto Saen

发明人： Futoshi FURUTA ,  Kenichi Osada ,  Makoto Saen

IPC分类号： H01L23/538 ,  H01L25/16

CPC分类号： H01L25/18 ,  G11C5/04 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

摘要翻译： 在以N级堆叠的半导体芯片的通孔通路中，在各半导体芯片中设置有中继电路。 例如，从半导体芯片的输出缓冲电路发送的信号经由各半导体芯片的中继电路发送到半导体芯片的输入缓冲电路。 各个中继器电路可以隔离输入侧和输出侧的阻抗，因此可以减少伴随着各个半导体芯片的通孔通路寄生的寄生电容的波形质量的劣化，并且可以降低高速信号 可以传输。

公开(公告)号：US20090251453A1

公开(公告)日：2009-10-08

申请号：US12417898

申请日：2009-04-03

申请人： Hiroshi Kageyama ,  Futoshi Furuta ,  Ken Takei

发明人： Hiroshi Kageyama ,  Futoshi Furuta ,  Ken Takei

IPC分类号： G09G5/00 ,  G02F1/1343

CPC分类号： G02F1/136286 ,  G02F1/1345 ,  G02F1/13452

摘要： In order to restrain increase in frame area caused along with a larger number of channels to a minimum, there is provided an image display device that adopts a communication method in which a signal is transmitted/received with the use of electrostatic capacitance coupling. A first board includes: a tabular first power supply line, a tabular second power supply line, a semiconductor element, and a tabular first electrode group. A second board includes: a tabular second electrode group and a tabular common electrode. In a state where the first board and the second board are laid on each other, the first electrode group overlaps the second electrode group while one of the first power supply line and the second power supply line overlaps the common electrode.

摘要翻译： 为了将更多数量的通道引起的帧区域的增加抑制到最小，提供了一种图像显示装置，其采用使用静电电容耦合来发送/接收信号的通信方法。 第一板包括：片状第一电源线，平板状第二电源线，半导体元件和平板状第一电极组。 第二板包括：片状第二电极组和平板状公共电极。 在第一板和第二板彼此铺设的状态下，第一电极组与第二电极组重叠，而第一电源线和第二电源线中的一个与公共电极重叠。

公开(公告)号：US07501877B2

公开(公告)日：2009-03-10

申请号：US11808337

申请日：2007-06-08

申请人： Futoshi Furuta ,  Kazuo Saitoh

发明人： Futoshi Furuta ,  Kazuo Saitoh

IPC分类号： H03K17/92

CPC分类号： H03K17/92 ,  H03K17/14 ,  H03K17/16 ,  H03M3/02 ,  H03M3/418 ,  H03M3/43 ,  H03M3/456

摘要： Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another. Moreover, by changing the density or phase of a SFQ pulse to be supplied to the Josephson junctions of the integration circuit, the correlativity of quantization noise between the outputs of the modulator circuits is eliminated so that the bit accuracy is improved.

摘要翻译： 本发明的目的是提供一种不产生积分泄漏的积分电路，使得在Σ-Δ调制电路或增量调制器电路中提高比特精度，该Δ-Δ调制电路或增量调制器电路基于使用通量量子的单通量量子电路 作为信息载体，并且提供减少热噪声和量化噪声的方法。 根据本发明，由约瑟夫逊结和电感器形成积分电路以减少积分泄漏，并且多个调制器电路彼此连接，以便将每个输出相加。 结果，可以减少施加在比特精度上的热噪声的影响，热噪声彼此不相关。 此外，通过改变要提供给积分电路的约瑟夫逊结的SFQ脉冲的密度或相位，消除了调制器电路的输出之间的量化噪声的相关性，从而提高了位精度。

公开(公告)号：US20080129368A1

公开(公告)日：2008-06-05

申请号：US11808337

申请日：2007-06-08

申请人： Futoshi Furuta ,  Kazuo Saitoh

发明人： Futoshi Furuta ,  Kazuo Saitoh

IPC分类号： H03K17/92

CPC分类号： H03K17/92 ,  H03K17/14 ,  H03K17/16 ,  H03M3/02 ,  H03M3/418 ,  H03M3/43 ,  H03M3/456

摘要： Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information carrier, and to provide a method for reducing thermal noise and quantization noise. According to the present invention, an integration circuit is formed by Josephson junctions and an inductor to reduce the integration leak, and a plurality of modulator circuits are connected to one another so as to add up each output. As a result, it is possible to reduce the influence of thermal noise exerted upon the bit accuracy, the thermal noise having no correlativity to one another. Moreover, by changing the density or phase of a SFQ pulse to be supplied to the Josephson junctions of the integration circuit, the correlativity of quantization noise between the outputs of the modulator circuits is eliminated so that the bit accuracy is improved.

摘要翻译： 本发明的目的是提供一种不产生积分泄漏的积分电路，使得在Σ-Δ调制电路或增量调制器电路中提高比特精度，该Δ-Δ调制电路或增量调制器电路基于使用通量量子的单通量量子电路 作为信息载体，并且提供减少热噪声和量化噪声的方法。 根据本发明，由约瑟夫逊结和电感器形成积分电路以减少积分泄漏，并且多个调制器电路彼此连接，以便将每个输出相加。 结果，可以减少施加在比特精度上的热噪声的影响，热噪声彼此不相关。 此外，通过改变要提供给积分电路的约瑟夫逊结的SFQ脉冲的密度或相位，消除了调制器电路的输出之间的量化噪声的相关性，从而提高了位精度。

公开(公告)号：US20100109096A1

公开(公告)日：2010-05-06

申请号：US12606812

申请日：2009-10-27

申请人： Kenichi Osada ,  Makoto Saen ,  Futoshi Furuta

发明人： Kenichi Osada ,  Makoto Saen ,  Futoshi Furuta

IPC分类号： H01L25/065

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/05552

摘要： A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias.

摘要翻译： 提供能够实现I / O处理性能提高，功耗降低，成本降低的半导体集成电路装置。 提供了一种半导体集成电路器件，其包括例如堆叠并安装的多个半导体芯片，具有通过通孔总线连接的数据收发终端的芯片和数据发送和接收通过总线使用最低的源 芯片的内部核心电路的电源电压之间的电压。 根据此，通过贯通孔将第n芯片的源极电压端子与源极电压端子连接，用于其他半导体芯片的数据收发电路。

公开(公告)号：US20100026950A1

公开(公告)日：2010-02-04

申请号：US12509602

申请日：2009-07-27

申请人： Futoshi FURUTA ,  Hiroshi Kageyama ,  Ken Takei

发明人： Futoshi FURUTA ,  Hiroshi Kageyama ,  Ken Takei

IPC分类号： G02F1/1343 ,  H01J1/62

CPC分类号： G02F1/1368 ,  G02F2001/134318 ,  G09G3/3225 ,  G09G3/3648 ,  G09G2300/0426

摘要： An image display device includes a display panel having plural pixels and a second board having a transmitting electrode, the display panel having a first substrate that is disposed so as to overlap the second board, each pixel having a pixel electrode and a counter electrode, and the counter electrode being formed in a planar shape and being commonly provided to the pixel electrodes of each pixel; the counter electrode being divided into a portion A corresponding to the transmitting electrode of the second board and a portion B other than it, and the portions A and B of the counter electrode being connected to a common voltage through resistors. The portion A of the counter electrode constitutes the receiving electrode, and the portion A of the counter electrode acting as the receiving electrode is connected to a receiving circuit in the display panel through a decoupling capacitor.

摘要翻译： 图像显示装置包括具有多个像素的显示面板和具有发送电极的第二基板，所述显示面板具有与所述第二基板重叠地配置的第一基板，每个像素具有像素电极和对置电极， 该对电极形成为平面形状，并且共同地设置在每个像素的像素电极上; 对置电极被分成对应于第二板的发送电极的部分A和除了它之外的部分B，并且对电极的部分A和B通过电阻器连接到公共电压。 对置电极的部分A构成接收电极，并且用作接收电极的对置电极的部分A通过去耦电容器连接到显示面板中的接收电路。