公开(公告)号：US12197840B2

公开(公告)日：2025-01-14

申请号：US17562728

申请日：2021-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/398 ,  G06F30/3312

Abstract: A technique for convergence verification including receiving a data object representation of a first circuit block, receiving one or more assumptions associated with the first circuit block, identifying a synchronization scheme coupled to a port of the first circuit block, determining that the synchronization scheme is within a threshold flip-flop depth, identifying, based on the determination that the synchronization scheme is within the threshold flip-flop depth, a type of the synchronization scheme and a flip-flop depth between the synchronization scheme and the port, generating first convergence information for the first circuit block based on the identified type and flip-flop depth of the synchronization scheme, and outputting the generated convergence information.

公开(公告)号：US11815971B2

公开(公告)日：2023-11-14

申请号：US17156910

申请日：2021-01-25

Applicant: Texas Instruments Incorporated

Inventor： Lakshmanan Balasubramanian ,  Aswani Kumar Golla ,  Venkatraman Ramakrishnan ,  Sushmitha Tudiyadka Girijashankar

IPC: G06F30/30 ,  G06F1/26 ,  G06F30/38 ,  H03K3/037

CPC classification number: G06F1/266 ,  G06F30/38 ,  H03K3/037

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.

公开(公告)号：US20230088503A1

公开(公告)日：2023-03-23

申请号：US18072842

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US20240256754A1

公开(公告)日：2024-08-01

申请号：US18103859

申请日：2023-01-31

Applicant: Texas Instruments Incorporated

Inventor： Atul Garg ,  Venkatraman Ramakrishnan

IPC: G06F30/398 ,  G06F1/10 ,  G06F30/396

CPC classification number: G06F30/398 ,  G06F1/10 ,  G06F30/396 ,  G06F2111/04

Abstract: A method and computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling. Based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. Clock skews for the CAPs associated with the plurality of elements are then scheduled as a function of the slack statistics. A refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the EDA tool.

公开(公告)号：US11775718B2

公开(公告)日：2023-10-03

申请号：US18072842

申请日：2022-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/02 ,  G06F117/04

CPC classification number: G06F30/3312 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F2117/04 ,  G06F2119/02

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US20240310868A1

公开(公告)日：2024-09-19

申请号：US18398496

申请日：2023-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory North ,  Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F1/06 ,  G06F1/08

CPC classification number: G06F1/06 ,  G06F1/08

Abstract: Embodiments disclosed herein relate to managing clock signals across clock domains. In one implementation, a system is configured to derive a base clock signal from a first clock trigger signal produced by a first subsystem in a first clock domain of the clocking system. The system is further configured to generate a second clock trigger signal based on the base clock signal and a main clock of a second subsystem in a second clock domain of the clocking system. The system is also configured to supply the second clock trigger signal to a second peripheral in the second clock domain.

公开(公告)号：US11531798B2

公开(公告)日：2022-12-20

申请号：US17246136

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/02 ,  G06F117/04

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US20220269845A1

公开(公告)日：2022-08-25

申请号：US17246136

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: G06F30/3312 ,  G06F30/327

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

公开(公告)号：US20240313749A1

公开(公告)日：2024-09-19

申请号：US18390818

申请日：2023-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gregory North ,  Sudhakar Surendran ,  Venkatraman Ramakrishnan

IPC: H03K5/00 ,  H03K3/037 ,  H03K5/133 ,  H03K21/10

CPC classification number: H03K5/00006 ,  H03K3/037 ,  H03K5/133 ,  H03K21/10

Abstract: Embodiments disclosed herein relate to the management of a multi-trim oscillator to provide synchronization across multiple frequencies derived from the multi-trim oscillator without causing spurious pulses of clock output. In one example, a system provides a first clock signal via an oscillator and a second clock signal based on the first clock signal and a divider. The system further receives a first signal that indicates a change in a frequency of the first clock signal from a first frequency to a second frequency. In response to the first signal, the system determines an edge of the second clock signal and provides, at a time based on the edge of the second clock signal, a second signal to the oscillator to cause the change to the second frequency.

公开(公告)号：US11574099B2

公开(公告)日：2023-02-07

申请号：US17393263

申请日：2021-08-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lakshmanan Balasubramanian ,  Venkatraman Ramakrishnan

IPC: G06F30/3308 ,  G06F30/327 ,  G06F30/323 ,  G06F30/337 ,  G06F30/367 ,  G06F30/373 ,  G06F119/06 ,  G06F119/18

Abstract: A method comprises creating an electronic module design having a plurality of electronic components and defining a model of functional behavior of a subset of the plurality of electronic components, the subset of the plurality of electronic components excluding a first electronic component. Functional behavior of the first electronic component is defined in a user-defined functional design intent file based on a first template, and a power behavior of the first electronic component is defined in a user-defined power design intent file based on a second template. A simulation file is generated based on the model of functional behavior and based on the functional behavior and the power behavior of the first electronic component. The simulation file is run to simulate operation of the electronic module design. A performance status is determined of the electronic module design in response to running the simulation file.