公开(公告)号：US12230678B2

公开(公告)日：2025-02-18

申请号：US17291842

申请日：2019-11-07

Applicant: The Regents of the University of California

Inventor： Umesh K. Mishra ,  Stacia Keller ,  Elaheh Ahmadi ,  Chirag Gupta ,  Yusuke Tsukada

IPC: H01L29/20 ,  H01L27/092 ,  H01L29/205 ,  H01L29/737 ,  H01L29/778 ,  H01L29/78 ,  H01L33/32

Abstract: The disclosure describes the use of strain to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition

公开(公告)号：US11588096B2

公开(公告)日：2023-02-21

申请号：US16092165

申请日：2017-04-11

Applicant: The Regents of the University of California

Inventor： Yuuki Enatsu ,  Chirag Gupta ,  Stacia Keller ,  Umesh K. Mishra ,  Anchal Agarwal

IPC: H01L41/18 ,  H01L33/08 ,  H01L29/36 ,  H01L29/861 ,  H01L29/20 ,  H01L29/205 ,  H01L21/00 ,  H01L41/107 ,  H01L21/02

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

公开(公告)号：US20190181329A1

公开(公告)日：2019-06-13

申请号：US16092165

申请日：2017-04-11

Applicant: The Regents of the University of California

Inventor： Yuuki Enatsu ,  Chirag Gupta ,  Stacia Keller ,  Umesh K. Mishra ,  Anchal Agarwal

IPC: H01L41/18 ,  H01L21/02 ,  H01L29/205 ,  H01L29/861 ,  H01L33/08 ,  H01L29/20 ,  H01L29/36

Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.

公开(公告)号：US10312361B2

公开(公告)日：2019-06-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20210399096A1

公开(公告)日：2021-12-23

申请号：US17291842

申请日：2019-11-07

Applicant: The Regents of the University of California

Inventor： Umesh K. Mishra ,  Stacia Keller ,  Elaheh Ahmadi ,  Chirag Gupta ,  Yusuke Tsukada

IPC: H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/737 ,  H01L27/092 ,  H01L29/78 ,  H01L33/32

Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.

公开(公告)号：US20170125574A1

公开(公告)日：2017-05-04

申请号：US15344377

申请日：2016-11-04

Applicant: The Regents of the University of California

Inventor： Srabanti Chowdhury ,  Jeonghee Kim ,  Chirag Gupta ,  Stacia Keller ,  Silvia H. Chan ,  Umesh K. Mishra

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L29/0623 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7788 ,  H01L29/7789 ,  H01L29/861

Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.

公开(公告)号：US20240063340A1

公开(公告)日：2024-02-22

申请号：US17642057

申请日：2020-09-10

Applicant: The Regents of the University of California

Inventor： Stacia Keller ,  Umesh K. Mishra ,  Shubhra Pasayat ,  Chirag Gupta

IPC: H01L33/32 ,  H01L33/16 ,  H01L33/12 ,  H01L25/075 ,  H01L33/20

CPC classification number: H01L33/32 ,  H01L33/16 ,  H01L33/12 ,  H01L25/0753 ,  H01L33/20

Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.